Vivado Synthesis Attribute

作者: 非鱼知乐 | 来源:发表于2020-08-10 08:40 被阅读0次

Vivado Synthesis Attribute
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Originated from UG901 v2020.1. Covers VHDL design only.

1. ASYN_REG

$\color{red}{Purpose}$ : To inform the tool that a register is capable of receiving asynchronous data in the D input pin relative to the source clock, or the register is a synchronizing register within a synchronization chain.
$\color{blue}{Where\ to\ define}$ : RTL or XDC

attribute ASYNC_REG : string;
attribute ASYNC_REG of sync_regs : signal is "TRUE";
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of sync_regs : signal is TRUE;

2. BLACK_BOX

$\color{red}{Purpose}$ : To turn a whole level of hierarchy off and create a black box for that entity.
$\color{blue}{Where\ to\ define}$ : RTL

attribute BLACK_BOX : string;
attribute BLACK_BOX of beh : architecutre is "yes";

3. CASCADE_HEIGHT

$\color{red}{Purpose}$ : To limit the length of cascade chains of large RAMs that are put into block RAMs.
$\color{blue}{Where\ to\ define}$ : RTL
$\color{yellow}{Note}$ : a value of 0 or 1 turns OFF any cascading of block RAMs.

attribute CASCADE_HEIGHT: integer;
attribute CASCADE_HEIGHT of ram: signal is 4;

4. CLOCK_BUFFER_TYPE

$\color{red}{Purpose}$ : To the type of clock buffer to use.
$\color{green}{Legal\ values}$ : "BUFG", "BUFH", "BUFIO", "BUFMR", "BUFR", "NONE".
$\color{blue}{Where\ to\ define}$ : RTL or XDC for top-level clock port.

-- define in VHDL
entity test is
    port
    (
        in1 : in std_logic;
        clock : in std_logic;
        out1 : out std_logic;
    );
    attribute CLOCK_BUFFER_TYPE: string;
    attribute CLOCK_BUFFER_TYPE of clock : signal is "BUFR";
end test;

# define in XDC
set_property CLOCK_BUFFER_TYPE BUFG [get_ports clk];

5. DIRECT_ENABLE

$\color{red}{Purpose}$ : To have an input port or a signal go directly to the enable line of a flop.
$\color{blue}{Where\ to\ define}$ : RTL or XDC for any port or signal.

-- define in VHDL
entity test is
    port
    (
        in1 : in std_logic;
        clock : in std_logic;
        en1, en2, en3 : in std_logic;
        out1 : out std_logic;
    );
    attribute DIRECT_ENABLE: string;
    attribute DIRECT_ENABLE of EN3: signal is "yes";
end test;

# define in XDC
set_property DIRECT_ENABLE  yes [get_nets -of [get_ports en3]];

6. DIRECT_RESET

$\color{red}{Purpose}$ : To have an input port or a signal go directly to the reset line of a flop.
$\color{blue}{Where\ to\ define}$ : RTL or XDC for any port or signal.

-- define in VHDL
entity test is
    port
    (
        in1 : in std_logic;
        clock : in std_logic;
        rst1, rst2 : in std_logic;
        out1 : out std_logic;
    );
    attribute DIRECT_RESET : string;
    attribute DIRECT_RESET of rst2 : signal is "yes";
end test;

# define in XDC
set_property DIRECT_ENABLE  yes [get_nets -of [get_ports rst2]];

7. DONT_TOUCH

$\color{red}{Purpose}$ : To replace KEEP or KEEP_HIERARCHY.
$\color{blue}{Where\ to\ define}$ : RTL. Only define it in XDC if remove DONT_TOUCH set to yes in RTL by setting it to no in XDC.

-- VHDL entity
entity test is
    port
    (
        in1 : in std_logic;
        clock : in std_logic;
        rst1, rst2 : in std_logic;
        out1 : out std_logic;
    );
    attribute DONT_TOUCH : string;
    attribute DONT_TOUCH of test : entity is "true|yes";
end test;

-- VHDL signal
signal sig1 : std_logic;
attribute DONT_TOUCH : string;
attribute DONT_TOUCH of test : entity is "true";
...
...
sig1 <= in1 and in2;
out1 <= sig1 and in3;

-- VHDL architecture
entity rtl of test is
    attribute DONT_TOUCH : string;
    attribute DONT_TOUCH of rtl : architecture is "yes";

-- VHDL component
entity rtl of test is
    attribute DONT_TOUCH : string;
    component my_comp
        port
        (
            in1 : in std_logic;
            out1 : out std_logic;
        );
    end component;
    attribute DONT_TOUCH of my_comp : component is "yes";

8. DSP_FOLDING

$\color{red}{Purpose}$ : To control whether to fold two MAC structures connected with an adder to one DSP primitive.
$\color{blue}{Where\ to\ define}$ : RTL.

-- VHDL example
attribute DSP_FOLDING : string;
attribute DSP_FOLDING of my_entity : entity is "yes";

9. DSP_FOLDING_FASTCLOCK

$\color{red}{Purpose}$ : To control which port should become the new faster clock when using DSP folding.
$\color{blue}{Where\ to\ define}$ : RTL on a port or a pin.

-- VHDL example
attribute DSP_FOLDING_FASTCLOCK : string;
attribute DSP_FOLDING of clock_fast : signal is "yes";

10. EXTRACT_ENABLE

$\color{red}{Purpose}$ : To control whether registers infer enables (go to CE pins) in case Vivado doesn't behave in a desired way.
$\color{blue}{Where\ to\ define}$ : RTL on registers.

-- VHDL example
signal my_reg : std_logic;
attribute EXTRACT_ENABLE : string;
attribute EXTRACT_ENABLE of my_reg : signal is "yes";

11. EXTRACT_RESET

$\color{red}{Purpose}$ : To control whether registers infer resets (go to R pins) in case Vivado doesn't behave in a desired way.
$\color{blue}{Where\ to\ define}$ : RTL on registers for synchronous resets.

-- VHDL example
signal my_reg : std_logic;
attribute EXTRACT_RESET : string;
attribute EXTRACT_RESET of my_reg : signal is "yes";

12. FSM_ENCODING

$\color{red}{Purpose}$ : To control encoding on FSM.
$\color{green}{Legal\ values}$ : "one_hot", "sequential", "johnson", "gray", "auto", and "none".
$\color{blue}{Where\ to\ define}$ : RTL or XDC.

-- VHDL example
typee state is (zero, one, two, three);
signal my_state : state;
attribute FSM_ENCODING : string;
attribute FSM_ENCODING of my_state : signal is "sequentiall";

13. FSM_SAFE_STATE

$\color{red}{Purpose}$ : To instruct Vivado to insert logic to the state machine to detect illegal states, then puts it into a known, good state on the next clock cycle.
$\color{green}{Legal\ values}$ : "auto_safe_state", "reset_state", "power_on_state", and "default_state" (an othhers state must be in the RTL).
$\color{blue}{Where\ to\ define}$ : RTL or XDC.

-- VHDL example
typee state is (zero, one, two, three);
signal my_state : state;
attribute FSM_SAFE_STATE : string;
attribute FSM_SAFE_STATE of my_state : signal is "power_on_state";

14. GATED_CLOCK

$\color{red}{Purpose}$ : To allow conversion of gated clocks
$\color{blue}{Where\ to\ define}$ : RTL on the signal or port that is the clock.

-- VHDL
entity test is
    port
    (
        in1, in2 : in std_logic;
        en : in std_logic;
        clk : in std_logic;
        out1 : out std_logic
    );
    attribute GATED_CLOCK : string;
    attribute GATED_CLOCK of clk : entity is "true|yes";
end test;

15. IOB

$\color{red}{Purpose}$ : To be used downstream by Vivado implementation to indicate if a register should go into the I/O buffer.
$\color{blue}{Where\ to\ define}$ : RTL on the register.

-- VHDL
signal sig1 : std_logic;
attribute IOB : string;
attribute IOB of sig1 : signal is "true";

16. IO_BUFFER_TYPE

$\color{red}{Purpose}$ : To use buffers for top-level ports.
$\color{blue}{Where\ to\ define}$ : RTL on top-level ports.

-- VHDL
entity test is
    port
    (
        in1, in2 : in std_logic;
        clk : in std_logic;
        out1 : out std_logic
    );
    attribute IO_BUFFER_TYPE: string;
    attribute IO_BUFFER_TYPEof out1 : signal is "none";
end test;

17. KEEP

$\color{red}{Purpose}$ : To prevent optimizations where signals are either optimized or absorbed into logic blocks. Can be used in conjunction with timing constraints when there is a timing constraint on a signal that would be optimized.
$\color{blue}{Where\ to\ define}$ : RTL on signals only.

-- VHDL
signal sig1 : std_logic;
attribute KEEP : string;
attribute KEEP of sig1 : signal is "true";
...
sig1 <= in1 and in2;
sig2 <= sig1 and in3;

18. KEEP_HIERARCHY

$\color{red}{Purpose}$ : To prevent optimization along the hierarchy boundaries
$\color{blue}{Where\ to\ define}$ : RTL and XDC in architecture level or the instance (mandatory for XDC).
$\color{yellow}{Note}$ : Should not be used on modules that describe the control logic of 3-state outputs and I/O buffers.

-- VHDL on architecture
attribute KEEP_HIERARCHY : string;
attribute KEEP_HIERARCHY of beh : entity is "yes";

# XDC on instance
set_property KEEP_HIERARCHY yes [get_cells u0]

19. MARK_DEBUG

$\color{red}{Purpose}$ : Applicable to net objects accessible to the internal array.
$\color{blue}{Where\ to\ define}$ : RTL and XDC on signals. In XDC, it is recommended to use set_property MARK_DEBUG true [get_nets -of [get_pins hier1/hier2/<flop_name>/Q to ensure it goes onto the net.

-- VHDL
signal dbg : std_logic;
attribute MARK_DEBUG : string;
attribute MARK_DEBUG of dbg : signal is "true";

# XDC on net
set_property MARK_DEBUG TRUE [get_nets dbg]

20. MAX_FANOUT

$\color{red}{Purpose}$ : To set fanout limit for registers and signals.
$\color{blue}{Where\ to\ define}$ : RTL on registers and combinational signals.
$\color{yellow}{Note}$ : Inpuut, black boxes, EDIF/EDF, and Native Generic Circuit (NGC) files are not supported.

-- VHDL
signal sig1 : std_logic;
attribute MAX_FANOUT : integer;
attribute MAX_FANOUT of sig1 : signal is 50;

21. RAM_DECOMP

$\color{red}{Purpose}$ : To instruct the tool to infer RTL RAMs that are too large to fit in a single block RAM primitive to use a more power friendly configuration. E.g., w/o RAM_DECOMP, a 2K x 36 is configured as two 2K x 18 BRAMs (fastest); w/ RAM_DECOMP, a 2K x 36 is configured as two 1K x 36 BRAMs (power-friendly)
$\color{green}{Legal\ values}$ : "power".
$\color{blue}{Where\ to\ define}$ :

-- VHDL
attribute RAM_DECOMP : string;
attribute RAM_DECOMP of my_ram : signal is "power";

# XDC
set_property RAM_DECOMP power [get_cells my_ram]

21. RAM_STYLE

$\color{red}{Purpose}$ : To instruct the tool on how to infer memory.
$\color{green}{Legal\ values}$ : "block" (BRAM), "distributed" (LUT RAM), "registers" (registers), and "ultra" (UltraScale+ URAM).
$\color{blue}{Where\ to\ define}$ : RTL and XDC.

-- VHDL
attribute RAM_STYLE : string;
attribute RAM_STYLE of my_ram : signal is "distributed";

# XDC
set_property RAM_DECOMP power [get_cells my_ram]

22. RETIMING_BACKWARD

$\color{red}{Purpose}$ : To move a register backwards through logic closer to the driving sequential elements.
$\color{green}{Legal\ values}$ : 0 (off), 1 (on).
$\color{yellow}{Note}$ : Not timing driven; will work regardless of whether the global timing setting is active or if there are timing constraints. RETIMING_BACKWARD is performed before timing. Cells with DONT_TOUCH/MARK_DEBUG attributes, cells with timing_exceptions (false_path, multicycle_path), and user-instantiated cells will block this attribute.

-- VHDL
attribute RETIMING_BACKWARD : string;
attribute RETIMING_BACKWARD of my_sig : signal is 1;

# XDC
set_property RETIMING_BACKWARD 1 power [get_cells my_sig]

23. RETIMING_FORWARD

$\color{red}{Purpose}$ : To move a register forward through logic closer to the driven sequential elements.
$\color{green}{Legal\ values}$ : 0 (off), 1 (on).
$\color{yellow}{Note}$ : Similar to RETIMING_BACKWARD.

-- VHDL
attribute RETIMING_FORWARD : string;
attribute RETIMING_FORWARD of my_sig : signal is 1;

# XDC
set_property RETIMING_FORWARD 1 power [get_cells my_sig]

24. ROM_STYLE

$\color{red}{Purpose}$ : To move a register forward through logic closer to the driven sequential elements.
$\color{green}{Legal\ values}$ : block (BRAM), distributed (LUT ROM).
$\color{blue}{Where\ to\ define}$ : RTL and XDC.
$\color{yellow}{Note}$ : Similar to RETIMING_BACKWARD.

-- VHDL
attribute ROM_STYLE : string;
attribute ROM_STYLE of my_rom : signal is "distributed";

25. RW_ADDR_COLLISION

$\color{red}{Purpose}$ : For specific types of RAMs. By default, when $rd\_addr=wr\_addr$ for DP_RAM, the output of the RAM is not guaranteed.
$\color{green}{Legal\ values}$ : "auto" (default), "yes" (insert bypass logic so that the value of the input will be on the output which behaves as WRITE_FIRST), and "no" (user doesn't care).
$\color{blue}{Where\ to\ define}$ : RTL.

-- VHDL
attribute RW_ADDR_COLLISION : string;
attribute RW_ADDR_COLLISIONof my_ram : signal is "yes";

26. SHREG_EXTRACT

$\color{red}{Purpose}$ : To infer SRL structures.
$\color{blue}{Where\ to\ define}$ : RTL and XDC.

-- VHDL
attribute SHREG_EXTRACT : string;
attribute SHREG_EXTRACT of my_srl : signal is "no";

27. SRL_STYLE

$\color{red}{Purpose}$ : To instruct Vivado on how to infer SRLs that are found in the design.
$\color{green}{Legal\ values}$ : "register", "srl", "srl_reg" (use an SRL and leave one register after the SRL), "reg_srl", "reg_srl_reg", "block" (use BRAM).
$\color{blue}{Where\ to\ define}$ : RTL and XDC.
$\color{yellow}{Note}$ : When used together, SHREG_EXTRACT takes precedence over SRL_STYLE and -shreg_min_size.

-- VHDL
attribute SRL_STYLE : string;
attribute SRL_STYLEof my_srl : signal is "reg_srl_reg";

# XDC
set_property SRL_STYLE register [get_cells my_shiftter_reg*]

28. TRANSLATE_OFF/TRANSLATE_ON

$\color{red}{Purpose}$ : To ignore blocks of code.
$\color{blue}{Where\ to\ define}$ : RTL.
$\color{yellow}{Note}$ : These attributes are given within a comment which should start with one of the keywords: synthesis, synopsys, pragma, xilinx. Simulation can still use the code.

-- VHDL
-- synthesis TRANSLATE_OFF
Code ...
-- synthesis TRANSLATE_ON

29. USE_DSP

$\color{red}{Purpose}$ : To deal with synthesis arithmetic structures (add, subtract, accumulat). By default, Vivado attempts to infer mults, mult-add, mult-sub, and mult-accumulate type structures into DSP blocks.
$\color{green}{Legal\ values}$ : logic (used specifically for XOR structures to go into DSP primitives. Can be placed on architecture level only), yes, no.
$\color{blue}{Where\ to\ define}$ : RTL and XDC.
$\color{yellow}{Note}$ : Yes and no can be placed on .

-- VHDL
attribute USE_DSP : string;
attribute USE_DSP of p_reg: signal is no;

30. Using synthesis attributes in XDC files

Format:

set_property <attribute> <value> <target>

For example:

set_property MAX_FANOUT 15 [get_cells in1_int_reg]

31. Synthesis attribute propagation rules

In general, an attribute placed on a hierarchy affects only that boundary, and will not affect the items inside that hierarchy.
Exceptions: DSP_FOLDING, RAM_STYLE, ROM_STYLE, SHREG_EXTRACT, and USE_DSP. When these attributes are placed on a hierarchy, they also affect the signals inside that hierarchy.

REFERENCE

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Vivado Synthesis Attribute

1. ASYN_REG

2. BLACK_BOX

3. CASCADE_HEIGHT

4. CLOCK_BUFFER_TYPE

5. DIRECT_ENABLE

6. DIRECT_RESET

7. DONT_TOUCH

8. DSP_FOLDING

9. DSP_FOLDING_FASTCLOCK

10. EXTRACT_ENABLE

11. EXTRACT_RESET

12. FSM_ENCODING

13. FSM_SAFE_STATE

14. GATED_CLOCK

15. IOB

16. IO_BUFFER_TYPE

17. KEEP

18. KEEP_HIERARCHY

19. MARK_DEBUG

20. MAX_FANOUT

21. RAM_DECOMP

21. RAM_STYLE

22. RETIMING_BACKWARD

23. RETIMING_FORWARD

24. ROM_STYLE

25. RW_ADDR_COLLISION

26. SHREG_EXTRACT

27. SRL_STYLE

28. TRANSLATE_OFF/TRANSLATE_ON

29. USE_DSP

30. Using synthesis attributes in XDC files

31. Synthesis attribute propagation rules

REFERENCE

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