FPGA实验案例

作者: finlu | 来源:发表于2018-07-26 23:47 被阅读0次

FPGA实验案例
FPGA串口通信失败可能的原因和解决方法
FPGA 自动售货机大作业
FPGA与HPS之间的通信实验 ——流水灯
在开始高速接口前，我们来试试IBERT测试吧
To Do List
fpga fifo
Verilog自制交通灯控制器加倒计时功能(内带源码文件)
使用Matlab生成COE文件
FPGA期末项目 | 数字时钟

本文适合刚开始接触 FPGA verilog语言的初学者阅读。能让初学者快速了解HDL语言的特性。从而更好，更快的进行硬件的开发。

流水灯实验

Sourse Design 文件

// flowing_light.v
`timescale 1ns / 1ps
module flowing_light(
    input clk,
    input rst,
    output [15:0] led
);
    
    reg [29:0] cnt_reg;
    reg [15:0] light_reg;
    
    // 例化IP核
    clk_wiz_0 clock1(
        // Clock out ports
        .clk_out1(clk_out1),     // output clk_out1
        // Status and control signals
        .resetn(rst), // input resetn
       // Clock in ports
        .clk_in1(clk)
       ); 
    
    // 当时钟的上升沿到来时或按下复位键的时候开始循环运行
    always @ (posedge clk_out1 or negedge rst) begin 
        if (!rst)
            cnt_reg <= 0;
        else if (cnt_reg >= 100000000)  // 系统的内置时钟为 100MHz，实现一秒记一次数的功能
            cnt_reg <= 0;
        else
            cnt_reg <= cnt_reg + 1;
    end
    
    // 
    always @ (posedge clk_out1 or negedge rst) begin
        if (!rst)
            light_reg <= 16'h0001;
        else if (cnt_reg == 29'd100000000) begin 
            if (light_reg == 16'h8000)
                light_reg <= 16'h0001;
            else
                light_reg <= light_reg << 1;   // 当第16个灯亮完之后，信号左移一位
            end
    end
    // 将 light_reg 的信号赋值给 led 输出
    assign led <= light_reg;   
endmodule

仿真文件

// flowing_light_tb.v
`timescale 1ns / 1ps

module flowing_light_tb;   // 申明当前所在模块

reg clk;  // 定义一个clk系统时钟寄存器 
reg rst;  // 定义一个复位的寄存器
    wire [15:0] led;   // 定义一个模拟16个led灯信号的wire类型变量
    
    // 例化 flowing_light 模块
    flowing_light inst(  
        .clk(clk), 
        .rst(rst), 
        .led(led) 
    ); 

initial begin 
    clk = 0;
    rst = 0;
    forever #5 clk=~clk;   // 循环：每隔 5ns 反向系统时钟信号
end 

initial begin 
    #100 rst = 1;   // 100 ns 后进行一次复位 
end  

endmodule

约束文件

// flowing_light.xdc
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports rst]
set_property PACKAGE_PIN F6 [get_ports {led[15]}]
set_property PACKAGE_PIN G4 [get_ports {led[14]}]
set_property PACKAGE_PIN G3 [get_ports {led[13]}]
set_property PACKAGE_PIN J4 [get_ports {led[12]}]
set_property PACKAGE_PIN H4 [get_ports {led[11]}]
set_property PACKAGE_PIN J3 [get_ports {led[10]}]
set_property PACKAGE_PIN J2 [get_ports {led[9]}]
set_property PACKAGE_PIN K2 [get_ports {led[8]}]
set_property PACKAGE_PIN K1 [get_ports {led[7]}]
set_property PACKAGE_PIN H6 [get_ports {led[6]}]
set_property PACKAGE_PIN H5 [get_ports {led[5]}]
set_property PACKAGE_PIN J5 [get_ports {led[4]}]
set_property PACKAGE_PIN K6 [get_ports {led[3]}]
set_property PACKAGE_PIN L1 [get_ports {led[2]}]
set_property PACKAGE_PIN M1 [get_ports {led[1]}]
set_property PACKAGE_PIN K3 [get_ports {led[0]}]

set_property PACKAGE_PIN P17 [get_ports clk]
set_property PACKAGE_PIN P15 [get_ports rst]
set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]

create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list clock1/inst/clk_out1]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
set_property port_width 28 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {cnt_reg_reg[0]} {cnt_reg_reg[1]} {cnt_reg_reg[2]} {cnt_reg_reg[3]} {cnt_reg_reg[4]} {cnt_reg_reg[5]} {cnt_reg_reg[6]} {cnt_reg_reg[7]} {cnt_reg_reg[8]} {cnt_reg_reg[9]} {cnt_reg_reg[10]} {cnt_reg_reg[11]} {cnt_reg_reg[12]} {cnt_reg_reg[13]} {cnt_reg_reg[14]} {cnt_reg_reg[15]} {cnt_reg_reg[16]} {cnt_reg_reg[17]} {cnt_reg_reg[18]} {cnt_reg_reg[19]} {cnt_reg_reg[20]} {cnt_reg_reg[21]} {cnt_reg_reg[22]} {cnt_reg_reg[23]} {cnt_reg_reg[24]} {cnt_reg_reg[25]} {cnt_reg_reg[26]} {cnt_reg_reg[27]}]]
create_debug_core u_ila_1 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_1]
set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_1]
set_property C_ADV_TRIGGER true [get_debug_cores u_ila_1]
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_1]
set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_1]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_1]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_1]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_1]
set_property port_width 1 [get_debug_ports u_ila_1/clk]
connect_debug_port u_ila_1/clk [get_nets [list clock1/inst/clkfbout_buf_clk_wiz_0]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe0]
set_property port_width 1 [get_debug_ports u_ila_1/probe0]
connect_debug_port u_ila_1/probe0 [get_nets [list rst_IBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
set_property port_width 16 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {led_OBUF[0]} {led_OBUF[1]} {led_OBUF[2]} {led_OBUF[3]} {led_OBUF[4]} {led_OBUF[5]} {led_OBUF[6]} {led_OBUF[7]} {led_OBUF[8]} {led_OBUF[9]} {led_OBUF[10]} {led_OBUF[11]} {led_OBUF[12]} {led_OBUF[13]} {led_OBUF[14]} {led_OBUF[15]}]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets u_ila_1_clkfbout_buf_clk_wiz_0]

二位比较器

Design Source 文件

// comp2bit.v
`timescale 1ns / 1ps

module comp2bit(
    input wire [1:0] a, 
    input wire [1:0] b, 
output wire a_eq_b,  
output wire a_gt_b,
output wire a_lt_b
);
assign a_eq_b=~b[1]& ~b[0]& ~a[1]& ~a[0]
                | ~b[1]& b[0]& ~a[1]& a[0]
                | b[1]& ~b[0]& a[1]& ~a[0]
                | b[1]& b[0]& a[1]& a[0];
assign a_gt_b=~b[1]& a[1]
                |~b[1]&~b[0]& a[0]
                |~b[0]& a[1]& a[0];
assign a_lt_b=b[1]& ~a[1]
                |b[1]& b[0]&~a[0]
                |b[0]&~a[1]&~a[0];
endmodule

仿真文件

// comp2bit_tb.v
`timescale 1ns / 1ps

module comp2bit_top;

    reg [1:0] a; 
    reg [1:0] b;
// 模拟三个输出结果    
wire a_eq_b;   
wire a_gt_b; 
wire a_lt_b;   

    // 例化 comp2bit 模块
    comp2bit inst ( 
        .a(a),  
        .b(b),  
        .a_eq_b(a_eq_b),  
        .a_gt_b(a_gt_b),  
        .a_lt_b(a_lt_b)  
    ); 

initial begin
    a=0;
    b=0;
    forever #30 a=~a;
end 

initial begin
    forever #60 b=~b;
end

endmodule

约束文件

// comp2bit.xdc
set_property PACKAGE_PIN P5 [get_ports {a[1]}]
set_property PACKAGE_PIN P4 [get_ports {a[0]}]
set_property PACKAGE_PIN N4 [get_ports {b[1]}]
set_property PACKAGE_PIN R1 [get_ports {b[0]}]
set_property PACKAGE_PIN H6 [get_ports a_eq_b]
set_property PACKAGE_PIN H5 [get_ports a_gt_b]
set_property PACKAGE_PIN K1 [get_ports a_lt_b]
set_property IOSTANDARD LVCMOS33 [get_ports {a[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {b[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {b[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports a_eq_b]
set_property IOSTANDARD LVCMOS33 [get_ports a_gt_b]
set_property IOSTANDARD LVCMOS33 [get_ports a_lt_b]

毛刺

Design Source文件

// mux21gr.v
`timescale 1ns / 1ps

module mux21gr(
    input wire a,  
    input wire b,
    input wire s,
    output wire y
);
wire nots; 
wire c; 
wire d; 
wire e;
assign #10nots=~s;
assign #10c=nots&a;
assign #10d=s&b;
assign #10e=a&b;
assign #10y=c|d|e;
endmodule

仿真文件

// mux21gr_tb.v
`timescale 1ns / 1ps

module mux21gr_tb;

reg a; 
reg b; 
reg s; 
wire y;

    mux21gr inst( 
        .a(a),  
        .b(b), 
        .s(s), 
        .y(y) 
    ); 
initial begin
    a=0;
    b=0;
    s=0;
    forever #200 s=~s;    // 勋魂：200ns延时后对s信号进行取反操作
end
initial begin
    #30 a=1;b=1;    // 只有当a为1的时候才会出现毛刺
end
endmodule

消除毛刺

Design Source文件

// mux21g.v
`timescale 1ns / 1ps

module mux21g(
    input  wire a,
    input  wire b,
    input  wire s,
    output wire  y
);
wire nots;
wire c;
wire d;

assign #10nots=~s;
assign #10c=nots&a;
assign #10d=s&b;
assign #10y=c|d;
endmodule

仿真文件

// mux21g_tb.v
`timescale 1ns / 1ps

module mux21g_tb;

reg a;
reg b;
reg s;
wire y;

    mux21g inst( 
        .a(a), 
        .b(b), 
        .s(s), 
        .y(y) 
    ); 
initial begin
    a=0;
    b=0;
    s=0;
    forever #200 s=~s;
end
initial begin
    #30 a=1;b=1;    // // 只有当a为1的时候才会出现毛刺 
end
endmodule

3 - 8 译码器

// decode38a.v
`timescale 1ns / 1ps

module decode38a(
input wire [2:0] a,
output wire [7:0] y
);

    // 逻辑关系实现 3-8 译码器
    assign y[0] = ~a[2]&~a[1]&~a[0]; 
    assign y[1] = ~a[2]&~a[1]& a[0]; 
    assign y[2] = ~a[2]& a[1]&~a[0]; 
    assign y[3] = ~a[2]& a[1]& a[0]; 
    assign y[4] =  a[2]&~a[1]&~a[0]; 
    assign y[5] = a[2]& ~a[1]& a[0]; 
    assign y[6] = a[2]& a[1]&~a[0]; 
    assign y[7] = a[2]& a[1]& a[0]; 

endmodule

// 使用for循环实现 3-8 译码器
/*
module decode38a (
    input wire[2:0] a,
    output reg[7:0] y
);
    integer i;
    always @(*) begin //******
        for (i=0;i<8;i=i+1) begin
            if (a==i)
                y[i]<=1;
            else y[i]<=0;
        end
    end
endmodule
*/

仿真文件

// decode38a_tb.v
`timescale 1ns / 1ps

module decode38a_tb;
    reg A,B,C;
    wire [7:0] y;
    wire [2:0] a;
    
    assign a={A,B,C};
    
    decode38a D( 
        .a(a),      
        .y(y) 
    ); 
    
    initial begin
        A=0;B=0;C=0;#100;   // a=0 
        A=0;B=0;C=1;#100;   // a=1
        A=0;B=1;C=0;#100;   // a=2
        A=0;B=1;C=1;#100;   // a=3
        A=1;B=0;C=0;#100;   // a=4
        A=1;B=0;C=1;#100;   // a=5
        A=1;B=1;C=0;#100;   // a=6
        A=1;B=1;C=1;#100;   // a=7
    end
endmodule

约束文件

// decode38a.xdc
set_property PACKAGE_PIN P5 [get_ports {a[2]}]
set_property PACKAGE_PIN P4 [get_ports {a[1]}]
set_property PACKAGE_PIN P3 [get_ports {a[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {y[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {y[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {y[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {y[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {y[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {y[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {y[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {y[0]}]
set_property PACKAGE_PIN K2 [get_ports {y[7]}]
set_property PACKAGE_PIN J2 [get_ports {y[6]}]
set_property PACKAGE_PIN J3 [get_ports {y[5]}]
set_property PACKAGE_PIN H4 [get_ports {y[4]}]
set_property PACKAGE_PIN J4 [get_ports {y[3]}]
set_property PACKAGE_PIN G3 [get_ports {y[2]}]
set_property PACKAGE_PIN G4 [get_ports {y[1]}]
set_property PACKAGE_PIN F6 [get_ports {y[0]}]

8 - 3 译码器

Design Source 文件

// encode38a.v
`timescale 1ns / 1ps

module encode38a(
input wire [7:0] x,
output reg [2:0] y,
output reg valid
);

integer i;

always @(*) begin
    y=0;
    valid=0;
    for(i=0;i<=7;i=i+1)
        if(x[i]==1) begin
            y=i;
            valid=1;
        end
end
    
/*
module encode38a(
input wire [7:0] x,
output wire [2:0] y,
output wire valid
);

// 逻辑实现 8-3 解码器
assign y[2]=x[7] | x[6] | x[5] | x[4];
assign y[1]=x[7] | x[6] | x[3] | x[2];
assign y[0]=x[7] | x[5] | x[3] | x[1];
assign valid = |x;

endmodule
*/

endmodule

仿真文件

// encode38_tb.v
`timescale 1ns / 1ps

module encode38_tb;

reg [7:0] x;
wire [2:0] y;
wire valid;

encode38a init(
    .x(x), 
    .y(y), 
    .valid(valid) 
);
wire dp;
assign dp=~valid;

initial begin
    #80 x[7]=~x[7];x[6]=~x[6];
    #10 x[7]=~x[7];
    $finish;
end

initial begin
    #70 x[6]=~x[6];x[5]=~x[5];
end

initial begin
    #60 x[5]=~x[5];x[4]=~x[4];
end

initial begin
    #50 x[4]=~x[4];x[3]=~x[3];
end

initial begin
    #40 x[3]=~x[3];x[2]=~x[2];
end

initial begin
    #30 x[2]=~x[2];x[1]=~x[1];
end

initial begin
    #20 x[1]=~x[1];x[0]=~x[0];
end

initial begin
    x=0;
    #10 x[0]=~x[0];    
end

endmodule

约束文件

// encode38a.xdc
set_property PACKAGE_PIN P5 [get_ports {x[0]}]
set_property PACKAGE_PIN P4 [get_ports {x[1]}]
set_property PACKAGE_PIN P3 [get_ports {x[2]}]
set_property PACKAGE_PIN P2 [get_ports {x[3]}]
set_property PACKAGE_PIN R2 [get_ports {x[4]}]
set_property PACKAGE_PIN M4 [get_ports {x[5]}]
set_property PACKAGE_PIN N4 [get_ports {x[6]}]
set_property PACKAGE_PIN R1 [get_ports {x[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {x[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {x[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {x[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {x[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {x[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {x[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {x[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {x[0]}]
set_property PACKAGE_PIN H5 [get_ports {y[2]}]
set_property PACKAGE_PIN H6 [get_ports {y[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {y[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {y[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {y[0]}]


set_property PACKAGE_PIN K3 [get_ports valid]
set_property IOSTANDARD LVCMOS33 [get_ports valid]
set_property PACKAGE_PIN K1 [get_ports {y[0]}]

4 位加法器

Design Source文件

`timescale 1ns / 1ps

// 相当于顶层模块
module adder4a(
    input wire clk,
    input wire [3:3] btn,
    input wire [7:0] sw,
    output wire [0:0] ld,
    output wire [6:0] a_to_g,
    output wire [3:0] an,
    output wire dp   // 数码管上的小数点 
);

    wire [15:0] x;
    wire cf;
    wire [3:0] s;

    assign x[15:12]=sw[7:4];
    assign x[11:8]=sw[3:0];
    assign x[7:4]={3'b000,cf};
    assign x[3:0]=s;
    
    adder4a_1 A1(
        .a(sw[7:4]), 
        .b(sw[3:0]), 
        .s(s), 
        .cf(cf), 
        .ovf(ld[0]) 
    ); 
            
     x7seg X1(
         .x(x), 
         .clk(clk), 
         .clr(btn[3]), 
         .a_to_g(a_to_g), 
         .an(an), 
         .dp(dp) 
              );
endmodule
    

module adder4a_1(
    input wire [3:0] a,
    input wire [3:0] b,
    output wire [3:0] s,
    output wire cf,
    output wire ovf
    );
    
    wire [4:0]c;
    
    assign c[0]=0;
    assign s=a^b^c[3:0];
    assign c[4:1]=a&b|c[3:0]&(a^b);
    assign cf=c[4];
    assign ovf=c[3]^c[4];
    
endmodule


module x7seg(
    input wire [15:0] x,
    input wire clk,
    input wire clr,
    output reg [6:0] a_to_g,
    output reg [3:0] an,
    output wire dp
    );
    wire [1:0] q;
    reg  [3:0] digit;
    wire [3:0] aen;
    reg  [19:0] clkdiv;
    assign dp=1;
    assign q=clkdiv[19:18];
    assign aen= 4'b0000;
    
            
   always@(*)
      case(q)
        0:digit=x[3:0];
        1:digit=x[7:4];
        2:digit=x[11:8];
        3:digit=x[15:12];        
        default:digit=x[3:0];
   endcase
   
    always@(*) 
        case(digit) 
            0:a_to_g=7'b1111110; 
            1:a_to_g=7'b0110000; 
            2:a_to_g=7'b1101101; 
            3:a_to_g=7'b1111001;
            4:a_to_g=7'b0110011;
            5:a_to_g=7'b1011011;
            6:a_to_g=7'b1011111;
            7:a_to_g=7'b1110000;
            8:a_to_g=7'b1111111;
            9:a_to_g=7'b1111011;
            'ha:a_to_g=7'b1110111;
            'hb:a_to_g=7'b0011111;
            'hc:a_to_g=7'b1001110;
            'hd:a_to_g=7'b0111101;
            'he:a_to_g=7'b1001111;
            'hf:a_to_g=7'b1000111;
            default:a_to_g=7'b1111110;
      endcase 
  
     
    always @(*) 
     begin 
    an=4'b0000; 
         if(aen[q]==0) 
             an[q]=1; 
     end    
    
    // 实时刷新的效果
    always@(posedge clk or  posedge clr) 
             begin 
                 if(!clr==1) 
                   clkdiv<=0;    
                else 
                   clkdiv<=clkdiv+1; 
                end         
endmodule

仿真文件

// adder4a_tb.v
`timescale 1ns / 1ps

module adder4a_tb;
     reg clk;
     reg [3:3]btn=1'b0;
     reg [7:0]sw;
     wire [0:0]ld;
     wire [6:0]a_to_g;
     wire [3:0]an;
     wire dp;
   
    adder4a inst( 
        .clk(clk), 
        .btn(btn), 
        .sw(sw), 
        .ld(ld), 
        .a_to_g(a_to_g), 
        .an(an), 
        .dp(dp)  
    ); 
    
initial begin  
      clk=0;
      btn=0; 
      forever #5 clk=~clk;    
end
    
always begin
     #10  sw=8'b00000001;
     #10  sw=8'b00010001;
     #10  sw=8'b00010010;
     #10 sw=8'b00100010;
     #10  sw=8'b00110010;  
end
    
endmodule

约束文件

// adder4a_tb.xdc
set_property PACKAGE_PIN B4 [get_ports {a_to_g[6]}]
set_property PACKAGE_PIN A4 [get_ports {a_to_g[5]}]
set_property PACKAGE_PIN A3 [get_ports {a_to_g[4]}]
set_property PACKAGE_PIN B1 [get_ports {a_to_g[3]}]
set_property PACKAGE_PIN A1 [get_ports {a_to_g[2]}]
set_property PACKAGE_PIN B3 [2356 {a_to_g[1]}]
set_property PACKAGE_PIN B2 [get_ports {a_to_g[0]}]
set_property PACKAGE_PIN G2 [get_ports {an[3]}]
set_property PACKAGE_PIN C2 [get_ports {an[2]}]
set_property PACKAGE_PIN C1 [get_ports {an[1]}]
set_property PACKAGE_PIN H1 [get_ports {an[0]}]
set_property PACKAGE_PIN P15 [get_ports {btn[3]}]
set_property PACKAGE_PIN K2 [get_ports {ld[0]}]
set_property PACKAGE_PIN P5 [get_ports {sw[7]}]
set_property PACKAGE_PIN P4 [get_ports {sw[6]}]
set_property PACKAGE_PIN P3 [get_ports {sw[5]}]
set_property PACKAGE_PIN P2 [get_ports {sw[4]}]
set_property PACKAGE_PIN R2 [get_ports {sw[3]}]
set_property PACKAGE_PIN M4 [get_ports {sw[2]}]
set_property PACKAGE_PIN N4 [get_ports {sw[1]}]
set_property PACKAGE_PIN R1 [get_ports {sw[0]}]
set_property PACKAGE_PIN P17 [get_ports clk]
set_property PACKAGE_PIN D5 [get_ports dp]
set_property IOSTANDARD LVCMOS33 [get_ports {a_to_g[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_to_g[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_to_g[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_to_g[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_to_g[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_to_g[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_to_g[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {btn[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ld[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports dp]

加/减法器

Design Source 文件

// addersub4.v
`timescale 1ns / 1ps

module addersub4(
    input wire [3:0] a,
    input wire [3:0] b,
    input wire E,
    output wire [3:0] s,
    output wire cf,
    output wire ovf
);

wire [4:0] c;
wire [3:0] bx;

assign bx=b^{4{E}};
assign c[0]=E;
assign s=a^bx^c[3:0];
assign c[4:1]=a&bx|c[3:0]&(a^bx);
assign cf=c[4];
assign ovf=c[3]^c[4];

endmodule

仿真文件

// addersub4_tb.v
`timescale 1ns / 1ps

module addersub4_tb;

    reg [3:0] a; 
    reg [3:0] b; 
reg E; 
    wire [3:0] s; 
wire cf;
wire ovf; 

    addersub4 init( 
        .a(a), 
        .b(b), 
        .E(E), 
        .s(s), 
        .cf(cf), 
        .ovf(ovf) 
    ); 

initial begin
    a=0;
    b=0;
    E=0;
    #0 a = 4'b0001; b = 4'b1010; E = 1'b0;  // 1 + 10  
    #5 a = 4'b1010; b = 4'b0010; E = 1'b1;  // 10 - 2
    #5 a = 4'b0010; b = 4'b1110; E = 1'b0;  // 2 + 15
    #5 a = 4'b1100; b = 4'b0011; E = 1'b1;  // 12 - 3
    #5 a = 4'b0111; b = 4'b1001; E = 1'b0;  // 7 + 9
    #5 a = 4'b1100; b = 4'b0101; E = 1'b1;  // 12 - 5
    #5 a = 4'b0011; b = 4'b1100; E = 1'b0;  // 3 + 12
    #5 a = 4'b0111; b = 4'b0101; E = 1'b1;  // 7 - 5
end
endmodule

乘法器

Design Source 文件

顶层文件

// mult4_top.v
`timescale 1ns / 1ps

module mult4_top(
    input wire clk,
    input wire [3:3] btn,
    input wire [7:0] sw,
    output wire [6:0] a_to_g,
    output wire [3:0] an,
    output wire dp
);

wire [15:0] x;
wire [7:0] p;
// get input from current module, and give the result to x[16:0]
assign x[15:12]=sw[7:4];
assign x[11:8]=sw[3:0];
assign x[7:0]=p;

mult4 M1(
    .a(sw[7:4]),
    .b(sw[3:0]),
    .p(p)
);

x7seg X1(
    .x(x),
    .clk(clk),
    .clr(btn),
    .a_to_g(a_to_g),
    .an(an),
    .dp(dp)
);

endmodule

被调用的模块一

// mult4.v
`timescale 1ns / 1ps

module mult4(
    input wire [3:0] a,
    input wire [3:0] b,
    output reg [7:0] p
);

reg [7:0] pv;
reg [7:0] ap;
integer i;

always @(*)
    begin
        pv=8'b00000000;
        ap={4'b0000,a};
        for(i=0;i<=7;i=i+1)
            begin
                if(b[i]==1)
                    pv=pv+ap;
                    ap={ap[6:0], 1'b0};
            end
        p=pv;
    end
    
endmodule

被调用的模块二

// x7seg.v
`timescale 1ns / 1ps

module x7seg(
    input wire [15:0] x,
    input wire clk,
    input wire clr,
    output reg [6:0] a_to_g,
    output reg [3:0] an,
    output wire dp
);

    wire [1:0] q;
    reg  [3:0] digit;
    wire [3:0] aen;
    reg  [19:0] clkdiv;
  
    assign dp=1;
    assign q=clkdiv[19:18];
    assign aen= 4'b0000;
              
   always@(*)
      case(q)
        0:digit=x[3:0];
        1:digit=x[7:4];
        2:digit=x[11:8];
        3:digit=x[15:12];        
        default:digit=x[3:0];
   endcase
   
    always@(*)
        case(digit)
            0:a_to_g=7'b1111110;
            1:a_to_g=7'b0110000;
            2:a_to_g=7'b1101101;
            3:a_to_g=7'b1111001;
            4:a_to_g=7'b0110011;
            5:a_to_g=7'b1011011;
            6:a_to_g=7'b1011111;
            7:a_to_g=7'b1110000;
            8:a_to_g=7'b1111111;
            9:a_to_g=7'b1111011;
            'ha:a_to_g=7'b1110111;
            'hb:a_to_g=7'b0011111;
            'hc:a_to_g=7'b1001110;
            'hd:a_to_g=7'b0111101;
            'he:a_to_g=7'b1001111;
            'hf:a_to_g=7'b1000111;
            default:a_to_g=7'b1111110;
        endcase
  
    always @(*)
        begin
            an=4'b0000;
            if(aen[q]==0)
                an[q]=1;
        end   
     
    always@(posedge clk or  posedge clr)
        begin
            if(!clr==1)
                clkdiv<=0;   
            else
                clkdiv<=clkdiv+1;
        end        
   
endmodule

仿真文件

`timescale 1ns / 1ps

module mult4_tb;
     reg clk;
     reg [3:3] btn=1'b0;
     reg [7:0] sw;
     wire [6:0] a_to_g;
     wire [3:0] an;
     wire dp;
   
    
    mult4_top inst( 
        .clk(clk), 
        .btn(btn), 
        .sw(sw),  
        .a_to_g(a_to_g), 
        .an(an), 
        .dp(dp) 
    ); 
    

    
initial begin
      clk=0; 
      btn=0;
      sw=0;
      forever #5 clk=~clk;    
end
    
always begin
     #10  sw=8'b00000001;  // 1
     #10  sw=8'b00010001;  // 17
     #10  sw=8'b00010010;  // 18
     #10  sw=8'b00100010;  // 34 
     #10  sw=8'b00110010;  // 50
end
    
endmodule

约束文件

// mult4.xdc
set_property PACKAGE_PIN B4 [get_ports {a_to_g[6]}]
set_property PACKAGE_PIN A4 [get_ports {a_to_g[5]}]
set_property PACKAGE_PIN A3 [get_ports {a_to_g[4]}]
set_property PACKAGE_PIN B1 [get_ports {a_to_g[3]}]
set_property PACKAGE_PIN A1 [get_ports {a_to_g[2]}]
set_property PACKAGE_PIN B3 [get_ports {a_to_g[1]}]
set_property PACKAGE_PIN B2 [get_ports {a_to_g[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_to_g[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_to_g[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_to_g[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_to_g[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_to_g[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_to_g[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_to_g[6]}]
set_property PACKAGE_PIN P15 [get_ports {btn[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {btn[3]}]
set_property PACKAGE_PIN P5 [get_ports {sw[7]}]
set_property PACKAGE_PIN P4 [get_ports {sw[6]}]
set_property PACKAGE_PIN P3 [get_ports {sw[5]}]
set_property PACKAGE_PIN P2 [get_ports {sw[4]}]
set_property PACKAGE_PIN R2 [get_ports {sw[3]}]
set_property PACKAGE_PIN M4 [get_ports {sw[2]}]
set_property PACKAGE_PIN N4 [get_ports {sw[1]}]
set_property PACKAGE_PIN R1 [get_ports {sw[0]}]
set_property PACKAGE_PIN P17 [get_ports clk]
set_property PACKAGE_PIN D5 [get_ports dp]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports dp]
set_property PACKAGE_PIN G2 [get_ports {an[3]}]
set_property PACKAGE_PIN C2 [get_ports {an[2]}]
set_property PACKAGE_PIN C1 [get_ports {an[1]}]
set_property PACKAGE_PIN H1 [get_ports {an[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]

4 位 ALU

Design Source 文件

// alu4.v
`timescale 1ns / 1ps

module alu4(
    input wire [2:0] alusel,
    input wire [3:0] a,
    input wire [3:0] b,
    output reg nf,
    output reg zf,
    output reg cf,
    // output reg ovf,
    output reg [3:0] y
);

reg [4:0] temp;

always @(*)
    begin
        cf=0;
        // ovf=0;
        temp=5'b00000;
        case(alusel)
            3'b000:y=a;
                3'b001:
                    begin
                        temp={1'b0,a} + {1'b0,b};
                        y=temp[3:0];
                        cf=temp[4];
                        // ovf=y[3]^a[3]^b[3]^cf;
                    end
                3'b010:
                    begin 
                        temp={1'b0,a} - {1'b0,b};
        y=temp[3:0];
                        cf=temp[4];
                        // ovf=y[3]^a[3]^b[3]^cf;
                    end
                3'b011:
                    begin
                        temp={1'b0,a} - {1'b0,b};
                        y=temp[3:0];
                        cf=temp[4];
                        // ovf=y[3]^a[3]^b[3]^cf;
                    end
                3'b100:y=~a;
                3'b101:y=a&b;
                3'b110:y=a|b;
                3'b111:y=a^b;
                default:y=a;
            endcase
            nf=y[3];
            if(y==4'b0000)
                zf=1;
            else
                zf=0;
        end
    
endmodule

仿真文件

module alu4_tb;

    reg [2:0] alusel; 
    reg [3:0] a; 
    reg [3:0] b; 
wire nf; 
wire zf;
wire cf;
// wire ovf;
    wire [3:0] y; 

    alu4 alu4_init ( 
        .alusel(alusel), 
        .a(a),  
        .b(b), 
        .nf(nf), 
        .zf(zf), 
        .cf(cf), 
        // .ovf(ovf), 
        .y(y) 
    ); 

initial begin
    alusel=0;
    a=4'b0101;   // 5
    b=4'b0011;   // 3
    #10 alusel=3'b000;  // 0
    #10 alusel=3'b001;  // 1
    #10 alusel=3'b010;  // 2
    #10 alusel=3'b011;  // 3
    #10 alusel=3'b100;  // 4
    #10 alusel=3'b101;  // 5
    #10 alusel=3'b110;  // 6
    #10 alusel=3'b111;  // 7
end

endmodule

7 段数码管静态显示

Design Source 文件

顶层文件

// x7seg_top.v
`timescale 1ns / 1ps

module x7seg_top(
    input wire [4:0] button,
    input wire clk,                                                 
    output wire [6:0] a_to_g,
    output wire  [3:0] an,
    output wire dp
);

wire  [15:0] x;
assign x='h5678;

    x7seg x1( 
        .button(button), 
        .x(x), 
        .clk(clk), 
        .a_to_g(a_to_g), 
        .an(an),  
        .dp(dp) 
    ); 

endmodule

被调用的模块

// x7seg.v
`timescale 1ns / 1ps

module x7seg(
    input wire [4:0] button,
    input wire [15:0] x,
    input wire clk,
    output reg [6:0] a_to_g,
    output reg [3:0] an,
    output wire dp
);

    wire [1:0] s;
    reg  [3:0] digit;
    wire [3:0] aen;
    reg  [19:0] clkdiv;
    reg [1:0] temp;
  
    assign dp=1;
    assign s=clkdiv[19:18];
    assign aen= 4'b0000;
              
   always@(*)
      case(s)
        0:digit=x[3:0];
        1:digit=x[7:4];
        2:digit=x[11:8];
        3:digit=x[15:12];        
        default:digit=x[3:0];
   endcase
   
    always@(*)
        case(digit)
            0:a_to_g=7'b1111110;
            1:a_to_g=7'b0110000;
            2:a_to_g=7'b1101101;
            3:a_to_g=7'b1111001;
            4:a_to_g=7'b0110011;
            5:a_to_g=7'b1011011;
            6:a_to_g=7'b1011111;
            7:a_to_g=7'b1110000;
            8:a_to_g=7'b1111111;
            9:a_to_g=7'b1111011;
            'ha:a_to_g=7'b1110111;
            'hb:a_to_g=7'b0011111;
            'hc:a_to_g=7'b1001110;
            'hd:a_to_g=7'b0111101;
            'he:a_to_g=7'b1001111;
            'hf:a_to_g=7'b1000111;
            default:a_to_g=7'b1111110;
        endcase

    always @(*)
        begin 
            an=aen;  
            if(button[4]==1)
                if (button[s]==1)
                    an[s]=1;
        end   
     
    always @(posedge clk)
        begin
            clkdiv<=clkdiv+1;
        end        
   
endmodule

约束文件

// x7seg.xdc
set_property PACKAGE_PIN B4 [get_ports {a_to_g[6]}]
set_property PACKAGE_PIN A4 [get_ports {a_to_g[5]}]
set_property PACKAGE_PIN A3 [get_ports {a_to_g[4]}]
set_property PACKAGE_PIN B1 [get_ports {a_to_g[3]}]
set_property PACKAGE_PIN A1 [get_ports {a_to_g[2]}]
set_property PACKAGE_PIN B3 [get_ports {a_to_g[1]}]
set_property PACKAGE_PIN B2 [get_ports {a_to_g[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_to_g[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_to_g[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_to_g[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_to_g[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_to_g[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_to_g[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_to_g[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
set_property PACKAGE_PIN G2 [get_ports {an[3]}]
set_property PACKAGE_PIN C2 [get_ports {an[2]}]
set_property PACKAGE_PIN C1 [get_ports {an[1]}]
set_property PACKAGE_PIN H1 [get_ports {an[0]}]
set_property PACKAGE_PIN P17 [get_ports clk]
set_property PACKAGE_PIN D5 [get_ports dp]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports dp]

set_property IOSTANDARD LVCMOS33 [get_ports {btn[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {btn[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {btn[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {btn[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {btn[0]}]
set_property PACKAGE_PIN R2 [get_ports {btn[4]}]
set_property PACKAGE_PIN P5 [get_ports {btn[3]}]
set_property PACKAGE_PIN P4 [get_ports {btn[2]}]
set_property PACKAGE_PIN P3 [get_ports {btn[1]}]
set_property PACKAGE_PIN P2 [get_ports {btn[0]}]

VGA 显示

Design Source 文件

顶层模块

`timescale 1ns / 1ps

module vga_stripes_top( 
    input wire mclk,
    input wire [3:0] btn, 
    output wire hsync, 
    output wire vsync, 
    output wire [2:0] red, 
    output wire [2:0] green,
    output wire [1:0] blue  
);

wire clk25,clr,vidon; 
    wire [9:0] hc,vc; 
    assign clr=btn[3]; 

    clkdiv U1( 
        .mclk(mclk), 
        .clr(clr), 
        .clk25(clk25) 
    ); 

    vga_640x480 U2( 
        .clk(clk25), 
        .clr(clr), 
        .hsync(hsync), 
        .vsync(vsync), 
        .hc(hc), 
        .vc(vc), 
        .vidon(vidon) 
    ); 

    vga_stripes U3( 
        .vidon(vidon), 
        .hc(hc), 
        .vc(vc), 
        .red(red), 
        .green(green), 
        .blue(blue) 
    ); 

endmodule

被调用的模块一

// clkdiv.v
module clkdiv(
    input wire mclk,
    input wire clr,
    output clk25
);

reg clk2;
reg [4:0] i;  

always @(posedge mclk or posedge clr)
    begin
        if(clr==1)begin
            clk2<=0;i<=0;
        end
        else begin
        if(i==1)begin
            clk2<=~clk2;i<=0;
        end
        else
        i<=i+1;
        end
        end
        assign clk25=clk2;    
endmodule

被调用的模块二

// vga_stripes.v
`timescale 1ns / 1ps

module vga_stripes(
    input wire vidon,
    input wire [9:0] hc,vc,
    output reg [2:0] red,green,
    output reg [1:0] blue
);

// shuchu 16 hangkuan de honglv tiaowen
always @(*)
    begin
        red=0;
        green=0;
        blue=0;
        if(vidon==1)
            begin
                red={vc[4],vc[4],vc[4]};
                green=~{vc[4],vc[4],vc[4]};
            end
    end
    
endmodule

被调用的模块三

`timescale 1ns / 1ps

module vga_640x480(
    input wire clk,
    input wire clr,
    output reg hsync,
    output reg vsync,
    output reg [9:0] hc,
    output reg [9:0] vc,
    output reg vidon
);

parameter hpixels=10'b1100100000;
parameter vlines=10'b1000001001;
parameter hbp=10'b0010010000;
parameter hfp=10'b1100010000;
parameter vbp=10'b0000011111;
parameter vfp=10'b0111111111;

reg vsenable;    // Enable for the Vertical counter


always @(posedge clk or posedge clr)
    begin
        if(clr==1)
            hc<=0;
        else
            begin
                if(hc==hpixels-1)
                    begin
                        // The counter has reached the end of pixel count
                        hc<=0;
                        vsenable<=1;
                        // Enable the vertical counter to increment
                    end
                else
                    begin
                        hc<=hc+1;  // Increment the horizontal counter
                        vsenable<=0;  // Leave the vensable off
                    end
            end
    end

// changshen hsync maichong
// dang hc wei 0~127shi,hang tongbu maichong wei didianpin
always @(*)
    begin
        if(hc<96)
            hsync=0;
        else
            hsync=1;
    end
    
// chang tongbu xinhao jishuqi
always @(posedge clk or posedge clr)
    begin
        if(clr==1)
            vc<=0;
        else
            if(vsenable==1)
                begin
                    if(vc==vlines-1)
                        // Reset when the number of line is reached
                        vc<=0;
                    else
                        vc<=vc+1;   // chang jishuqi jia 1
                end
    end
    
// changshen vsync maichong
// dang hc wei 0 hui 1 shi,chang tongbu maichong wei didianping
always @(*)
    begin
        if(vc<2)
            vsync=0;
        else
            vsync=1;
    end
    
    
// Enable video out when within the porches
always @(*)
    begin
        if((hc<hfp)&&(hc>hbp)&&(vc<vfp)&&(vc>vbp))
            vidon=1;
        else
            vidon=0;
    end
   
endmodule

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FPGA实验案例

流水灯实验

Sourse Design 文件

仿真文件

约束文件

二位比较器

Design Source 文件

仿真文件

约束文件

毛刺

Design Source文件

仿真文件

消除毛刺

Design Source文件

仿真文件

3 - 8 译码器

仿真文件

约束文件

8 - 3 译码器

Design Source 文件

仿真文件

约束文件

4 位加法器

Design Source文件

仿真文件

约束文件

加/减法器

Design Source 文件

仿真文件

乘法器

Design Source 文件

顶层文件

被调用的模块一

被调用的模块二

仿真文件

约束文件

4 位 ALU

Design Source 文件

仿真文件

7 段数码管静态显示

Design Source 文件

顶层文件

被调用的模块

约束文件

VGA 显示

Design Source 文件

顶层模块

被调用的模块一

被调用的模块二

被调用的模块三

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