Computer Abstractions and Techno

接上一次记录，芯片的初始形态，是圆形的晶圆（wafer），如下图：

将圆形变成方形，肯定就意味着损失 —— 为了减小损失，就要缩小芯片的尺寸，在这里对应着工艺：

The cost of an integrated circuit rises quickly as the die size increases, due both to the lower yield and to the fewer dies that fit on a wafer. To reduce the cost, using the next generation process shrinks a large die as it uses smaller sizes for both transistors and wires. This improves the yield and the die count per wafer. A 32-nanometer (nm) process was typical in 2012, which means essentially that the smallest feature size on the die is 32nm.

这带来的结果是几个公式：

第一个是数学逻辑，定义性质的了；第二个是近似，因为还是有边缘上的损失；第三个是经验公式，因此成本与芯片面积并不是线性关系：

Hence, depending on the defect rate and the size of the die and wafer, costs are generally not linear in the die area.