非阻塞赋值起作用在 @posedge clk 之后

module aw_top();

logic                                 clk;
logic                                 rstn;

initial begin
  clk = 0;
  forever begin
    #1ns;
    clk = ~clk;
  end
end
initial begin
  rstn = 0;
  #100ns;
  rstn = 1;
end

bit[1:0]                            bid;
bit                                 bvalid;

bit[3-1:0]                          write_vld;
bit[3-1:0]                          write_ready;
bit[3*32-1:0 ]                      write_start_adr;
bit[3*4-1:0 ]                       write_len;
bit[3*32-1:0 ]                      write_dat;
bit[3-1:0]                          write_lst;
bit[3*(32/8) -1:0]                  write_strb;


AXI_XXX #(
  .AXI_ADR_W(32),
  .AXI_DAT_W(32),
  .AXI_LEN_W(4),
  .MAX_REQ_NUM(2),
  .MASTER_NUM(3),
  .AXI_ID_W(2)
) dut_inst(

  .clk                        (clk),
  .rst_n                      (rstn),
  .axi_write_adapter_clr      (1'b0),
  
  .write_return_err           (),
  .bus_ok                     (),

  .write_ready                (write_ready),
  .write_vld                  (write_vld      ),
  .write_start_adr            (write_start_adr),
  .write_len                  (write_len      ),
  .write_dat                  (write_dat      ),
  .write_lst                  (write_lst      ),
  .write_strb                 (write_strb     ),

  .reg_awqos                   (12'b0),
  .awid                        (),
  .awaddr                      (),
  .awlen                       (),
  .awsize                      (),
  .awburst                     (),
  .awlock                      (),
  .awcache                     (),
  .awprot                      (),
  .awqos                       (),
  .awvalid                     (),
  .awready                     (1'b1),
  
  //AXI Write Data Channel
  .wid                         (),
  .wdata                       (),
  .wstrb                       (),
  .wlast                       (),
  .wvalid                      (),
  .wready                      (1'b1),

  //AXI Write Response Channel
  .bid                        (bid),
  .bresp                      (2'b0),
  .bvalid                     (bvalid),
  .bready                     ()
);

initial begin
  wait(rstn==1);
  repeat(10)  @(posedge clk);
  for(int i=0; i<3; i++) begin
    automatic int cnt=0;
    automatic int idx=i;
    automatic bit rand_vld;
    automatic bit[3:0] rand_len;
    automatic int len_cnt=0;
    fork
      while(cnt<10) begin
        @(posedge clk);
        write_vld[idx] <= 1'b0;
        std::randomize(rand_vld);
        if(idx!=0) rand_vld = 0;
        std::randomize(rand_len);
        @(posedge clk);
        if(rand_vld) begin
          $display("%t, idx[%d]: rand_len is %d", $realtime, idx, rand_len);
          do begin
            write_vld[idx] <= 1'b1;
            write_len[idx*4 +: 4] <= rand_len;
            write_lst[idx] <= 1'b0;
            write_start_adr[idx*32 +: 32]  <= $urandom();
            write_dat[idx*32 +: 32]        <= $urandom();
            write_strb[idx*4 +: 4]       <= $urandom();
            if(len_cnt==rand_len)
              write_lst[idx] <= 1'b1;
            @(posedge clk);
            if(write_vld[idx] & write_ready[idx])   len_cnt = len_cnt + 1;
          end while(len_cnt<(rand_len+1));
          write_lst[idx] <= 1'b0;
          write_vld[idx] <= 1'b0;
          fork
            begin
              repeat($urandom_range(2,10)) begin
                @(posedge clk);
              end
              bvalid <= 1'b1;
              bid <= idx;
              @(posedge clk);
              bvalid <= 1'b0;
              @(posedge clk);
              cnt = cnt + 1;
              $display("%t, idx[%d], cnt is %d", $realtime, idx, cnt);
            end
          join_none
        end
        @(posedge clk);
        len_cnt = 0;
      end
    join_none
  end
end

initial begin
  #10000ns;
  $finish;
end


  initial begin
    $fsdbDumpfile("aw_top.fsdb");
    $fsdbDumpvars(0, "aw_top");
  end
endmodule



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