By writing to the screen we have actually already encountered a friendlier form of hard-
ware I/O, known as memory-mapped I/O, whereby data written directly to a certain
address range in main memory is written to the device's internal memory buffer, but
now it is time to understand more about this interaction between CPU and hardware.
Let's take the now-popular TFT monitor as an example. The screen's surface is
divided up into a matrix of backlit cells. By containing a layer of liquid crystals sand-
wiched between polarised film, the amount of light passing through each cell can be
varied by the application of an electric field, since liquid crystals have the property that,
when subjected to an electrical field, their orientation may be altered in a consistent
manner; as the orientation of the crystals changes, they alter the light wave's direction
of vibration, such that some of the light will be blocked by the polarised film at the
screen's surface. For a colour display, each cell is further divided into three areas that
are overlaid with lters for red, blue, and green .
So it is the hardware's job to ensure that the appropriate cells, or sub-cell colour
areas, get subjected to appropriate electrical field to reconstruct the desired image on the
screen.This side of hardware is best left to specialist electronic engineers, but there will
be a controller chip, ideally with well defined functionality that is described in the chip's
datasheet, on the device or motherboard with which the CPU can interact to direct
the hardware.
Internally, controller chips usually have several registers that can be read, written or
both by the CPU, and it is the state of these registers that tell the controller what to
do (e.g. what pins to set high or low to drive the hardware, or what internal function to
perform).
As an example, from the datasheet of Intel's widely used 82077AA single-chip
floppy disk controller , we see there is a pin (pin 57, labelled ME0) that drives the motor
of the first floppy disk device (since a single controller can drive several such devices):
when the pin is on, the motor spins;when off, the motor does not spin. The state of
this particular pin is directly linked to a particular bit of the controller's internal register
named the Digital Output Register (DOR). The state of that register can then be set by
setting a value, with the appropriate bit set (bit 4, in this case), across the chip's data
pins, labelled DB0--DB7, and using the chip's register selection pins, A0--A2, to select
the DOR register by its internal address 0x2.
6.1.1 I/O Buses
Although historically the CPU would talk directly to device controllers, with ever in-
creasing CPU speeds, that would require the CPU artificially to slow down to the same
speed as the slowest device, so it is more practical for the CPU to issue I/O instructions
directly to the controller chip of a high-speed, top-level bus. The bus controller is then
responsible for relaying, at a compatible rate, the instructions to a particular device's
controller. Then to avoid the top-level bus having to slow down for slower devices, the
controller of a another bus technology may be added as a device, such that we arrive at
the hierarchy of buses found in modern computers .
6.1.2 I/O Programming
So the question is, how do we read and write the registers of our device controllers (i.e.
tell our devices what to do) programatically? In Intel architecture systems the registers
of device controllers are mapped into an I/O address space, that is seperate from the main
memory address space, then varients of the I/O instructions in and out are used to read
and write data to the I/O addresses that are mapped to specific controller registers. For
example, the floppy disk controller descibed earlier usually has its DOR register mapped to
I/O address 0x3F2, so we could switch on the motor of the first drive with the following
instructions:
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