3个状态机
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity state_one is
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
x : in STD_LOGIC;
z : out STD_LOGIC
);
end state_one;
--}} End of automatically maintained section
architecture three of state_one is
signal cs:std_logic_vector(1 downto 0);
signal ns:std_logic_vector(1 downto 0);
constant s1:std_logic_vector(1 downto 0):="00";
constant s2:std_logic_vector(1 downto 0):="01";
constant s3:std_logic_vector(1 downto 0):="11";
begin
process(clk,reset)
begin
if(clk'event and clk='1') then
if reset='1' then
cs<="00";
else
cs<=ns;
end if;
end if;
end process;
process(x,clk)
begin
case cs is
when "00"=>
if(x='0') then
ns<="00";
z<='0';
end if;
if(x='1') then
ns<="01";
z<='1';
end if;
when "01"=>
if (x='0')then
ns<="11";
z<='1';
end if;
if (x='1')then
ns<="01";
z<='0';
end if;
when "11"=>
if(x='0') then
ns<="00";
z<='0';
end if;
if(x<='1') then
ns<="00";
z<='1';
end if;
when others=>
ns<="00";
z<='0';
end case;
end process;
-- enter your statements here --
end three;
4、library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity stete_four is
port(
clk : in STD_LOGIC;
x : in STD_LOGIC;
reset : in STD_LOGIC;
z : out STD_LOGIC
);
end stete_four;
--}} End of automatically maintained section
architecture four of stete_four is
signal cs:std_logic_vector(3 downto 0);
signal ns:std_logic_vector(3 downto 0);
constant s1:std_logic_vector(3 downto 0):="1001";
constant s2:std_logic_vector(3 downto 0):="0010";
constant s3:std_logic_vector(3 downto 0):="0101";
constant s4:std_logic_vector(3 downto 0):="1010";
constant s5:std_logic_vector(3 downto 0):="0100";
begin
process(clk,reset)
begin
if(clk'event and clk='1') then
if(reset<='1') then
cs<="1001";
else
cs<=ns;
end if;
end if;
end process;
process(clk,x)
begin
case cs is
when "1001"=>
if(x='1') then
ns<="1001";
end if;
if (x='0') then
ns<="0010";
end if;
when "0010"=>
if(x='1') then
ns<="0101";
end if;
if (x='0') then
ns<="0100";
end if;
when "0101"=>
if(x='1') then
ns<="0101";
end if;
if (x='0') then
ns<="1010";
end if;
when "1010"=>
if(x='1') then
ns<="0101";
end if;
if (x='0') then
ns<="0100";
end if;
when "0100"=>
if(x='1') then
ns<="1001";
end if;
if (x='0') then
ns<="0100";
end if;
when others=>
ns<="1000";
end case;
end process;
process(clk,x)
begin
case cs is
when"1001"=>
if(x='0') then
z<='1';
else
z<='0';
end if;
when others=>
z<='0';
end case;
end process;
-- enter your statements here --
end four;
5、library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity state is
port(
tck : in STD_LOGIC;
tms : in STD_LOGIC;
reset : in STD_LOGIC;
up_dr : out STD_LOGIC
);
end state;
--}} End of automatically maintained section
architecture five of state is
type state_type is(TLR,RT,SDS,CD,SD,ED1,PD,ED2,UD);
signal cs,ns:state_type;
signal x:std_logic;
begin
x<=tms;
process(tck,reset)
begin
if(tck'event and tck='1') then
if (reset='1') then
cs<=TLR;
else
cs<=ns;
end if;
end if;
end process;
process(x,cs)
begin
case cs is
when TLR=>
if(x='1') then
ns<=TLR;
end if;
if(x='0') then
ns<=RT;
end if;
when RT=>
if(x='1') then
ns<=SDS;
end if;
if(x='0') then
ns<=RT;
end if;
when SDS=>
if(x='1') then
ns<=TLR;
end if;
if(x='0') then
ns<=CD;
end if;
when CD=>
if(x='1') then
ns<=ED1;
end if;
if(x='0') then
ns<=SD;
end if;
when SD=>
if(x='1') then
ns<=ED1;
end if;
if(x='0') then
ns<=SD;
end if;
when ED1=>
if(x='1') then
ns<=UD;
end if;
if(x='0') then
ns<=PD;
end if;
when PD=>
if(x='1') then
ns<=ED2;
end if;
if(x='0') then
ns<=PD;
end if;
when ED2=>
if(x='1') then
ns<=UD;
end if;
if(x='0') then
ns<=SD;
end if;
when UD=>
if(x='1') then
ns<=SDS;
end if;
if(x='0') then
ns<=RT;
end if;
when others=>
ns<=TLR;
end case;
end process;
process(cs,x)
begin
case cs is
when UD=>
up_dr<='1';
when others =>
up_dr<='0';
end case;
end process;
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