IDS

there are four parts in top level block of this design:   fast clock counter, state clock counter,  7-segment switch and segment display.  the workflow is : fast clock signal will access to the fast counter ,  which is 16 a counter and used for decode of segment, in the meanwhile, it provides signal for swtich part whose function is switch among four segments，finally，the state clock signal go to scout part, and it can control five states of segment display，which can change every half second

fast counter

in the beginning, fast clock signal will access to the fast counter ,  which is 16 a counter and used for decode of segment. it contains four D flop, there are four number pin and 16 output, reset pin is controled by state counter, and the states table and sch are as follows

stater counter

the internal architecture of this part is same as fast counter except clock signal frequency, there are three D flop，it function is to control five states of segment display，which can change every half second,  it connects one and gate, which can send signal to reset fast count part when it become 111， the sch is showed in

switch part

this part is used for decode of 7-segment, which is to change among four number segments, its archticture is four D flop and