Distributed RAM的写地址

看Distributed RAM的时候，发现一个奇怪的地方，写地址位数比读地址位数多，如下图：

ram256x1s.jpg

整个RAM256x1S的读写地址都是8位(A[7:0])，这是好理解的，2^8=256，总共支持256个地址。但是它内部的SPRAM64的读地址是6位(A[6:1])，写地址是8位(WA[8:1])，就不好理解了。

直觉上，一个SPRAM64支持64个地址，读写地址应该都是6位。整个RAM256x1S包含4个SPRAM64，总共支持256个地址。

对于读，比较好理解，外部的A[7:0]中的低6位连接到的SPRAM64的A[6:1]，高2位连接到右侧的mux，用于在4个SPRAM64中选择一个做为最终的输出。

对于写，外部的A[7:0]直接连到SPRAM64的WA[8:1]，好像一个SPRAM64就支持256个地址一样，不太好理解。
如果对于写，在左侧也有几个mux，根据A[7:0]的高2位分别使能不同的SPRAM64(WE)，就比较好理解了。

经过一番搜索，通过bing在xilinx官网找到了一个帖子：
https://forums.xilinx.com/t5/Virtex-Family-FPGAs-Archived/Address-port-of-a-Single-port-Distributed-RAM-RAM256X1S/td-p/143038
其中提到：

1. How does the configured LUT write the input data (DI1) to the address in the SPRAM64 using the write address port WA[8:1] and address port A[6:1]?

The 8-bit WA write address addresses all 4 LUTs (SPRAM64s) in the SLICEM, not just one of them.  The 8-bit address selects 1 of 256 locations to be written from the D input to the SLICEM.  Six of the eight WA bits select an individual location in each SPRAM64 block, and two of the eight WA bits are decoded to enable writing to only one of the four SPRAM64 blocks when the SLICEM is configured as a single 256-bit RAM.

2. Is there any decoder inside the configured LUT to distinguish addresses?
Xilinx is famous for diagrams which are representative of the function, and not necessarily representative of the implementation.  Do not infer more detail in the diagram than Xilinx intends to represent.  Accept the notion that eight WA address bits are used to select and enable one (and only one) bit location of the four 64-bit SPRAM64 blocks.

2. Is there any decoder inside the configured LUT to distinguish addresses?

Of course.  Otherwise it wouldn't function as a 64bit (or 256bit) RAM.

从这个帖子来看，就是每个SPRAM64都会对8位的写地址进行解码。比如首个SPRAM64，只有当WA[8:7]为2'b00时才会真正写入，第二个SPRAM64，只有当WA[8:7]为2'b01时才会真正写入，依此类推。