实验5-2：四选一数据选择器（数据流描述）

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    14:40:10 11/15/2018 
// Design Name: 
// Module Name:    Trial_52 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Trial_52(
    A,B,C,D,S,Y,EN
     );

input [1:0] A,B,C,D,S;
output [1:0] Y;
input EN;
wire[1:0] A,B,C,D,S,Y;
wire EN;

assign Y[1]=(~EN)&(((~S[1])&(~S[0])&A[1])|((~S[1])&S[0]&B[1])|(S[1]&(~S[0])&C[1])|(S[1]&S[0]&D[1]));
assign Y[0]=(~EN)&(((~S[1])&(~S[0])&A[0])|((~S[1])&S[0]&B[0])|(S[1]&(~S[0])&C[0])|(S[1]&S[0]&D[0]));



endmodule

管脚约束文件

NET "EN"        LOC = T3;
NET "S[1]"      LOC = U3;
NET "S[0]"      LOC = T4;
NET "A[1]"      LOC = V3;
NET "A[0]"      LOC = V4;
NET "B[1]"      LOC = W4;
NET "B[0]"      LOC = Y4;
NET "C[1]"      LOC = Y6;
NET "C[0]"      LOC = W7;
NET "D[1]"      LOC = Y8;
NET "D[0]"      LOC = Y7;
NET "Y[1]"      LOC = R1;
NET "Y[0]"      LOC = P2;

NET "EN"        IOSTANDARD = LVCMOS18;
NET "S[1]"      IOSTANDARD = LVCMOS18;
NET "S[0]"      IOSTANDARD = LVCMOS18;
NET "A[1]"      IOSTANDARD = LVCMOS18;
NET "A[0]"      IOSTANDARD = LVCMOS18;
NET "B[1]"      IOSTANDARD = LVCMOS18;
NET "B[0]"      IOSTANDARD = LVCMOS18;
NET "C[1]"      IOSTANDARD = LVCMOS18;
NET "C[0]"      IOSTANDARD = LVCMOS18;
NET "D[1]"      IOSTANDARD = LVCMOS18;
NET "D[0]"      IOSTANDARD = LVCMOS18;
NET "Y[1]"      IOSTANDARD = LVCMOS18;
NET "Y[0]"      IOSTANDARD = LVCMOS18;

NET "EN"        PULLDOWN;
NET "S[1]"      PULLDOWN;
NET "S[0]"      PULLDOWN;
NET "A[1]"      PULLDOWN;
NET "A[0]"      PULLDOWN;
NET "B[1]"      PULLDOWN;
NET "B[0]"      PULLDOWN;
NET "C[1]"      PULLDOWN;
NET "C[0]"      PULLDOWN;
NET "D[1]"      PULLDOWN;
NET "D[0]"      PULLDOWN;