一、所需环境
- 首先下载官方版本：
官网下载地址ftp://ftp.denx.de/pub/u-boot/u-boot-2017.11.tar.bz2。 - 安装交叉编译工具链
笔者采用Ubuntu18进行开发，可以直接输入sudo apt install gcc-arm-linux-gnueabihf直接安装。安装后输入arm-linux-gnueabihf-gcc -v，有如下结果说明安装成功：
Using built-in specs.
COLLECT_GCC=arm-linux-gnueabihf-gcc
COLLECT_LTO_WRAPPER=/usr/lib/gcc-cross/arm-linux-gnueabihf/7/lto-wrapper
Target: arm-linux-gnueabihf
...
Thread model: posix
gcc version 7.3.0 (Ubuntu/Linaro 7.3.0-27ubuntu1~18.04)
- 安装设备树编译工具
较新的uboot也采用设备树来管理设备，需要安装device-tree-compiler，命令如下：
$ sudo apt install device-tree-compiler
$ dtc -v
$ Version: DTC 1.4.5
二、开始移植
1. 参考资料
由于itop4412与Samsung官方的origen开发板所用CPU一致，很大一部分是通用的，可以参考一下。
再参考一下某大佬的博客iTop-4412精英版的u-boot-2017.11移植教程。下面是对移植较新版的uboot留下的笔记。
2.拷贝origen下的可重用代码框架
- 拷贝board下的origen目录，名为itop4412
$ cp board/samsung/origen/ board/samsung/itop4412 -r
$ tree board/samsung/itop4412
itop4412
├── itop4412.c
├── Kconfig
├── MAINTAINERS
├── Makefile
└── tools
└── mkitop4412spl.c
- 拷贝include/configs/origen.h，命名为itop4412.h
$ cp include/configs/origen.h include/configs/itop4412.h
- 拷贝arch/arm/dts/exynos4412-odroid.dts
$ cd arch/arm/dts/
$ cp exynos4412-odroid.dts exynos4412-itop4412.dts
3.修改board/samsung/itop4412下的文件
- Kconfig
if TARGET_ITOP4412
config SYS_BOARD
default "itop4412"
config SYS_VENDOR
default "samsung"
config SYS_CONFIG_NAME
default "itop4412"
endif
- Makefile
ifdef CONFIG_SPL_BUILD
# necessary to create built-in.o
obj- := __dummy__.o
hostprogs-y := tools/mkitop4412spl
always := $(hostprogs-y)
# omit -O2 option to suppress
# warning: dereferencing type-punned pointer will break strict-aliasing rules
#
# TODO:
# Fix the root cause in tools/mkitop4412spl.c and delete the following work-around
$(obj)/tools/mkitop4412spl: HOSTCFLAGS:=$(filter-out -O2,$(HOSTCFLAGS))
else
obj-y += itop4412.o
endif
4.增加machine-type标识
在arch/arm/include/asm/mach-types.h文件中的if与endif之间添加宏
#define MACH_TYPE_ITOP4412 5115
5.修改mach-exynos目录下的Kconfig
在文件前部分添加如下内容
config TARGET_ITOP4412
bool "Exynos4412 iTop-4412 board"
select SUPPORT_SPL
末尾添加：
source "board/samsung/itop4412/Kconfig"
三、编译说明
- 指定编译的arch和工具链
顶层Makefile中有如下几行：
# set default to nothing for native builds
ifeq ($(HOSTARCH),$(ARCH))
CROSS_COMPILE ?=
endif
在编译时指定ARCH和CROSS_COMPILE变量的值或者手动在Makefile中指定皆可。这里笔者采用手动定义变量的方法：
$ make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-
以上步骤做完后，便可以编译出来一个u-boot.bin的文件。
四、对板子做适配
由于使用的Itop4412与origen开发板还是有很多差异的，下面总结常见的需要修改的地方。
1. 编写默认的defconfig文件
参考二-1. 参考资料中的链接中的文章，采用经过验证的默认配置，如下：
1 CONFIG_ARM=y
2 CONFIG_ARCH_EXYNOS=y
3 CONFIG_ARCH_EXYNOS4=y
4 CONFIG_TARGET_ITOP4412=y
5 CONFIG_SPL_GPIO_SUPPORT=y
6 CONFIG_SPL_SERIAL_SUPPORT=y
7 CONFIG_IDENT_STRING=" for itop-4412"
8 CONFIG_DEFAULT_DEVICE_TREE="exynos4412-itop4412"
9 CONFIG_DEBUG_UART=y
10 CONFIG_SD_BOOT=y
11 CONFIG_BOOTDELAY=5
12 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
13 CONFIG_SYS_CONSOLE_INFO_QUIET=y
14 CONFIG_SPL=y
15 CONFIG_HUSH_PARSER=y
16 CONFIG_SYS_PROMPT="u-boot # "
17 CONFIG_CMD_BOOTZ=y
18 # CONFIG_CMD_XIMG is not set
19 CONFIG_CMD_THOR_DOWNLOAD=y
20 CONFIG_CMD_DFU=y
21 # CONFIG_CMD_FPGA is not set
22 CONFIG_CMD_GPT=y
23 CONFIG_CMD_MMC=y
24 CONFIG_CMD_PART=y
25 CONFIG_CMD_USB_MASS_STORAGE=y
26 # CONFIG_CMD_NET is not set
27 CONFIG_CMD_DHCP=y
28 # CONFIG_CMD_NFS is not set
29 CONFIG_CMD_MII=y
30 CONFIG_CMD_CACHE=y
31 # CONFIG_CMD_MISC is not set
32 CONFIG_CMD_EXT2=y
33 CONFIG_CMD_EXT4=y
34 CONFIG_CMD_EXT4_WRITE=y
35 CONFIG_CMD_FAT=y
36 CONFIG_CMD_FS_GENERIC=y
37 CONFIG_ISO_PARTITION=y
38 CONFIG_OF_CONTROL=y
39 CONFIG_OF_EMBED=y
40 CONFIG_DFU_MMC=y
41 CONFIG_DM_MMC=y
42 CONFIG_MMC_DW=y
43 CONFIG_MMC_SDHCI=y
44 CONFIG_MMC_SDHCI_SDMA=y
45 CONFIG_MMC_SDHCI_S5P=y
46 CONFIG_DEBUG_UART_S5P=y
47 CONFIG_DEBUG_UART_BASE=0x13820000
48 CONFIG_DEBUG_UART_CLOCK=100000000
49 CONFIG_USB=y
50 CONFIG_DM_USB=y
51 CONFIG_USB_GADGET=y
52 CONFIG_USB_GADGET_MANUFACTURER="Samsung"
53 CONFIG_USB_GADGET_VENDOR_NUM=0x04e8
54 CONFIG_USB_GADGET_PRODUCT_NUM=0x6601
55 CONFIG_USB_GADGET_DWC2_OTG=y
56 CONFIG_USB_GADGET_DOWNLOAD=y
2. 编写itop4412_setup.h
定义itop4412开发板对应的宏，保存在arch/arm/mach-exynos/itop4412_setup.h中。定义方法类似与arch/arm/mach-exynos/exynos4_setup.h类似，参阅Samsung官方的4412手册，具体查阅时钟初始化章节。下面贴出代码，以后有时间再仔细分析：
/*
* Machine Specific Values for EXYNOS4412 based board
*
* Copyright (C) 2011 Samsung Electronics
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ITOP4412_SETUP_H
#define _ITOP4412_SETUP_H
#include <config.h>
#include <asm/arch/cpu.h>
#ifdef CONFIG_CLK_800_330_165
#define DRAM_CLK_330
#endif
#ifdef CONFIG_CLK_1000_200_200
#define DRAM_CLK_200
#endif
#ifdef CONFIG_CLK_1000_330_165
#define DRAM_CLK_330
#endif
#ifdef CONFIG_CLK_1000_400_200
#define DRAM_CLK_400
#endif
/* this state is changing for register */
#define MUX_STAT_CHANGING 0x100
#define DIV_STAT_CHANGING 0x1
/* A/M/EV PLL_CON0 */
#define SDIV(x) ((x) & 0x7)
#define PDIV(x) (((x) & 0x3f) << 8)
#define MDIV(x) (((x) & 0x3ff) << 16)
#define FSEL(x) (((x) & 0x1) << 27)
#define PLL_LOCKED_BIT (0x1 << 29)
#define PLL_ENABLE(x) (((x) & 0x1) << 31)
/* A/M PLL_CON1 */
#define AFC(x) ((x) & 0x1f)
#define LOCK_CON_DLY(x) (((x) & 0x1f) << 8)
#define LOCK_CON_IN(x) (((x) & 0x3) << 12)
#define LOCK_CON_OUT(x) (((x) & 0x3) << 14)
#define FEED_EN(x) (((x) & 0x1) << 16)
#define AFC_ENB(x) (((x) & 0x1) << 20)
#define DCC_ENB(x) (((x) & 0x1) << 21)
#define BYPASS(x) (((x) & 0x1) << 22)
#define RESV0(x) (((x) & 0x1) << 23)
#define RESV1(x) (((x) & 0x1) << 24)
/* E/V PLL_CON1 */
#define K(x) ((x) & 0xffff)
#define MFR(x) (((x) & 0xff) << 16)
#define MRR(x) (((x) & 0x1f) << 24)
#define SEL_PF(x) (((x) & 0x3) << 29)
/* E/V PLL_CON2 */
#define ICP_BOOST(x) ((x) & 0x3)
#define EV_FSEL(x) (((x) & 0x1) << 2)
#define FVCO_EN(x) (((x) & 0x1) << 3)
#define EV_BYPASS(x) (((x) & 0x1) << 4)
#define SSCG_EN(x) (((x) & 0x1) << 5)
#define EV_AFC_ENB(x) (((x) & 0x1) << 6)
#define EV_DCC_ENB(x) (((x) & 0x1) << 7)
#define EXTAFC(x) (((x) & 0x1f) << 8)
/* CLK_SRC_CPU */
#define MUX_APLL_SEL(x) ((x) & 0x1)
#define MUX_CORE_SEL(x) (((x) & 0x1) << 16)
#define MUX_HPM_SEL(x) (((x) & 0x1) << 20)
#define MUX_MPLL_USER_SEL_C(x) (((x) & 0x1) << 24)
/* CLK_MUX_STAT_CPU */
#define APLL_SEL(x) ((x) & 0x7)
#define CORE_SEL(x) (((x) & 0x7) << 16)
#define HPM_SEL(x) (((x) & 0x7) << 20)
#define MPLL_USER_SEL_C(x) (((x) & 0x7) << 24)
#define MUX_STAT_CPU_CHANGING (APLL_SEL(MUX_STAT_CHANGING) | \
CORE_SEL(MUX_STAT_CHANGING) | \
HPM_SEL(MUX_STAT_CHANGING) | \
MPLL_USER_SEL_C(MUX_STAT_CHANGING))
/* A/M/E/V PLL_LOCK */
#define PLL_LOCKTIME(x) ((x) & 0xffff)
/* CLK_DIV_CPU0 */
#define CORE_RATIO(x) ((x) & 0x7)
#define COREM0_RATIO(x) (((x) & 0x7) << 4)
#define COREM1_RATIO(x) (((x) & 0x7) << 8)
#define PERIPH_RATIO(x) (((x) & 0x7) << 12)
#define ATB_RATIO(x) (((x) & 0x7) << 16)
#define PCLK_DBG_RATIO(x) (((x) & 0x7) << 20)
#define APLL_RATIO(x) (((x) & 0x7) << 24)
#define CORE2_RATIO(x) (((x) & 0x7) << 28)
/* CLK_DIV_CPU1 */
#define COPY_RATIO(x) ((x) & 0x7)
#define HPM_RATIO(x) (((x) & 0x7) << 4)
#define CORES_RATIO(x) (((x) & 0x7) << 8)
/* CLK_DIV_STAT_CPU0 */
#define DIV_CORE(x) ((x) & 0x1)
#define DIV_COREM0(x) (((x) & 0x1) << 4)
#define DIV_COREM1(x) (((x) & 0x1) << 8)
#define DIV_PERIPH(x) (((x) & 0x1) << 12)
#define DIV_ATB(x) (((x) & 0x1) << 16)
#define DIV_PCLK_DBG(x) (((x) & 0x1) << 20)
#define DIV_APLL(x) (((x) & 0x1) << 24)
#define DIV_CORE2(x) (((x) & 0x1) << 28)
#define DIV_STAT_CPU0_CHANGING (DIV_CORE(DIV_STAT_CHANGING) | \
DIV_COREM0(DIV_STAT_CHANGING) | \
DIV_COREM1(DIV_STAT_CHANGING) | \
DIV_PERIPH(DIV_STAT_CHANGING) | \
DIV_ATB(DIV_STAT_CHANGING) | \
DIV_PCLK_DBG(DIV_STAT_CHANGING) | \
DIV_APLL(DIV_STAT_CHANGING) | \
DIV_CORE2(DIV_STAT_CHANGING))
/* CLK_DIV_STAT_CPU1 */
#define DIV_COPY(x) ((x) & 0x1)
#define DIV_HPM(x) (((x) & 0x1) << 4)
#define DIV_CORES(x) (((x) & 0x1) << 8)
#define DIV_STAT_CPU1_CHANGING (DIV_COPY(DIV_STAT_CHANGING) | \
DIV_HPM(DIV_STAT_CHANGING) | \
DIV_CORES(DIV_STAT_CHANGING))
/* CLK_SRC_DMC */
#define MUX_C2C_SEL(x) ((x) & 0x1)
#define MUX_DMC_BUS_SEL(x) (((x) & 0x1) << 4)
#define MUX_DPHY_SEL(x) (((x) & 0x1) << 8)
#define MUX_MPLL_SEL(x) (((x) & 0x1) << 12)
#define MUX_PWI_SEL(x) (((x) & 0xf) << 16)
#define MUX_G2D_ACP0_SEL(x) (((x) & 0x1) << 20)
#define MUX_G2D_ACP1_SEL(x) (((x) & 0x1) << 24)
#define MUX_G2D_ACP_SEL(x) (((x) & 0x1) << 28)
/* CLK_MUX_STAT_DMC */
#define C2C_SEL(x) ((x) & 0x7)
#define DMC_BUS_SEL(x) (((x) & 0x7) << 4)
#define DPHY_SEL(x) (((x) & 0x7) << 8)
#define MPLL_SEL(x) (((x) & 0x7) << 12)
#define G2D_ACP0_SEL(x) (((x) & 0x7) << 20)
#define G2D_ACP1_SEL(x) (((x) & 0x7) << 24)
#define G2D_ACP_SEL(x) (((x) & 0x7) << 28)
#define MUX_STAT_DMC_CHANGING (C2C_SEL(MUX_STAT_CHANGING) | \
DMC_BUS_SEL(MUX_STAT_CHANGING) | \
DPHY_SEL(MUX_STAT_CHANGING) | \
MPLL_SEL(MUX_STAT_CHANGING) |\
G2D_ACP0_SEL(MUX_STAT_CHANGING) | \
G2D_ACP1_SEL(MUX_STAT_CHANGING) | \
G2D_ACP_SEL(MUX_STAT_CHANGING))
/* CLK_DIV_DMC0 */
#define ACP_RATIO(x) ((x) & 0x7)
#define ACP_PCLK_RATIO(x) (((x) & 0x7) << 4)
#define DPHY_RATIO(x) (((x) & 0x7) << 8)
#define DMC_RATIO(x) (((x) & 0x7) << 12)
#define DMCD_RATIO(x) (((x) & 0x7) << 16)
#define DMCP_RATIO(x) (((x) & 0x7) << 20)
/* CLK_DIV_DMC1 */
#define G2D_ACP_RATIO(x) ((x) & 0xf)
#define C2C_RATIO(x) (((x) & 0x7) << 4)
#define PWI_RATIO(x) (((x) & 0xf) << 8)
#define C2C_ACLK_RATIO(x) (((x) & 0x7) << 12)
#define DVSEM_RATIO(x) (((x) & 0x7f) << 16)
#define DPM_RATIO(x) (((x) & 0x7f) << 24)
/* CLK_DIV_STAT_DMC0 */
#define DIV_ACP(x) ((x) & 0x1)
#define DIV_ACP_PCLK(x) (((x) & 0x1) << 4)
#define DIV_DPHY(x) (((x) & 0x1) << 8)
#define DIV_DMC(x) (((x) & 0x1) << 12)
#define DIV_DMCD(x) (((x) & 0x1) << 16)
#define DIV_DMCP(x) (((x) & 0x1) << 20)
#define DIV_STAT_DMC0_CHANGING (DIV_ACP(DIV_STAT_CHANGING) | \
DIV_ACP_PCLK(DIV_STAT_CHANGING) | \
DIV_DPHY(DIV_STAT_CHANGING) | \
DIV_DMC(DIV_STAT_CHANGING) | \
DIV_DMCD(DIV_STAT_CHANGING) | \
DIV_DMCP(DIV_STAT_CHANGING))
/* CLK_DIV_STAT_DMC1 */
#define DIV_G2D_ACP(x) ((x) & 0x1)
#define DIV_C2C(x) (((x) & 0x1) << 4)
#define DIV_PWI(x) (((x) & 0x1) << 8)
#define DIV_C2C_ACLK(x) (((x) & 0x1) << 12)
#define DIV_DVSEM(x) (((x) & 0x1) << 16)
#define DIV_DPM(x) (((x) & 0x1) << 24)
#define DIV_STAT_DMC1_CHANGING (DIV_G2D_ACP(DIV_STAT_CHANGING) | \
DIV_C2C(DIV_STAT_CHANGING) | \
DIV_PWI(DIV_STAT_CHANGING) | \
DIV_C2C_ACLK(DIV_STAT_CHANGING) | \
DIV_DVSEM(DIV_STAT_CHANGING) | \
DIV_DPM(DIV_STAT_CHANGING))
/* CLK_SRC_TOP0 */
#define MUX_ONENAND_1_SEL(x) ((x) & 0x1)
#define MUX_EPLL_SEL(x) (((x) & 0x1) << 4)
#define MUX_VPLL_SEL(x) (((x) & 0x1) << 8)
#define MUX_ACLK_200_SEL(x) (((x) & 0x1) << 12)
#define MUX_ACLK_100_SEL(x) (((x) & 0x1) << 16)
#define MUX_ACLK_160_SEL(x) (((x) & 0x1) << 20)
#define MUX_ACLK_133_SEL(x) (((x) & 0x1) << 24)
#define MUX_ONENAND_SEL(x) (((x) & 0x1) << 28)
/* CLK_MUX_STAT_TOP */
#define ONENAND_1_SEL(x) ((x) & 0x3)
#define EPLL_SEL(x) (((x) & 0x3) << 4)
#define VPLL_SEL(x) (((x) & 0x3) << 8)
#define ACLK_200_SEL(x) (((x) & 0x3) << 12)
#define ACLK_100_SEL(x) (((x) & 0x3) << 16)
#define ACLK_160_SEL(x) (((x) & 0x3) << 20)
#define ACLK_133_SEL(x) (((x) & 0x3) << 24)
#define ONENAND_SEL(x) (((x) & 0x3) << 28)
#define MUX_STAT_TOP0_CHANGING (ONENAND_1_SEL(MUX_STAT_CHANGING) | \
EPLL_SEL(MUX_STAT_CHANGING) | \
EPLL_SEL(MUX_STAT_CHANGING) | \
VPLL_SEL(MUX_STAT_CHANGING) | \
ACLK_200_SEL(MUX_STAT_CHANGING) | \
ACLK_100_SEL(MUX_STAT_CHANGING) | \
ACLK_160_SEL(MUX_STAT_CHANGING) | \
ACLK_133_SEL(MUX_STAT_CHANGING) | \
ONENAND_SEL(MUX_STAT_CHANGING))
/* CLK_SRC_TOP1 */
#define MUX_ACLK_266_GPS_SEL(x) (((x) & 0x1) << 4)
#define MUX_ACLK_400_MCUISP_SEL(x) (((x) & 0x1) << 8)
#define MUX_MPLL_USER_SEL_T(x) (((x) & 0x1) << 12)
#define MUX_ACLK_266_GPS_SUB_SEL(x) (((x) & 0x1) << 16)
#define MUX_ACLK_200_SUB_SEL(x) (((x) & 0x1) << 20)
#define MUX_ACLK_400_MCUISP_SUB_SEL(x) (((x) & 0x1) << 24)
/* CLK_MUX_STAT_TOP1 */
#define ACLK_266_GPS_SEL(x) (((x) & 0x3) << 4)
#define ACLK_400_MCUISP_SEL(x) (((x) & 0x3) << 8)
#define MPLL_USER_SEL_T(x) (((x) & 0x3) << 12)
#define ACLK_266_GPS_SUB_SEL(x) (((x) & 0x3) << 16)
#define ACLK_200_SUB_SEL(x) (((x) & 0x3) << 20)
#define ACLK_400_MCUISP_SUB_SEL(x) (((x) & 0x3) << 24)
#define MUX_STAT_TOP1_CHANGING (MUX_ACLK_266_GPS_SEL(MUX_STAT_CHANGING) | \
ACLK_400_MCUISP_SEL(MUX_STAT_CHANGING) | \
MPLL_USER_SEL_T(MUX_STAT_CHANGING) | \
ACLK_266_GPS_SUB_SEL(MUX_STAT_CHANGING) | \
ACLK_200_SUB_SEL(MUX_STAT_CHANGING) | \
ACLK_400_MCUISP_SUB_SEL(MUX_STAT_CHANGING))
/* CLK_DIV_TOP */
#define ACLK_200_RATIO(x) ((x) & 0x7)
#define ACLK_100_RATIO(x) (((x) & 0xf) << 4)
#define ACLK_160_RATIO(x) (((x) & 0x7) << 8)
#define ACLK_133_RATIO(x) (((x) & 0x7) << 12)
#define ONENAND_RATIO(x) (((x) & 0x7) << 16)
#define ACLK_266_GPS_RATIO(x) (((x) & 0x7) << 20)
#define ACLK_400_MCUISP_RATIO(x) (((x) & 0x7) << 24)
#define DIV_STAT_TOP_CHANGING (ACLK_400_MCUISP_RATIO(DIV_STAT_CHANGING) | \
ACLK_266_GPS_RATIO(DIV_STAT_CHANGING) | \
ONENAND_RATIO(DIV_STAT_CHANGING) | \
ACLK_133_RATIO(DIV_STAT_CHANGING) | \
ACLK_160_RATIO(DIV_STAT_CHANGING) | \
ACLK_100_RATIO(DIV_STAT_CHANGING) | \
ACLK_200_RATIO(DIV_STAT_CHANGING))
/* CLK_SRC_LEFTBUS */
#define MUX_GDL_SEL(x) ((x) & 0x1)
#define MUX_MPLL_USER_SEL_L(x) (((x) & 0x1) << 4)
/* CLK_MUX_STAT_LEFTBUS */
#define GDL_SEL(x) ((x) & 0x7)
#define MPLL_USER_SEL_L(x) (((x) & 0x7) << 4)
#define MUX_STAT_LEFTBUS_CHANGING (GDL_SEL(MUX_STAT_CHANGING) | \
MPLL_USER_SEL_L(MUX_STAT_CHANGING))
/* CLK_DIV_LEFTBUS */
#define GDL_RATIO(x) ((x) & 0x7)
#define GPL_RATIO(x) (((x) & 0x7) << 4)
/* CLK_DIV_STAT_LEFTBUS */
#define DIV_GDL(x) ((x) & 0x1)
#define DIV_GPL(x) (((x) & 0x1) << 4)
#define DIV_STAT_LEFTBUS_CHANGING (DIV_GDL(DIV_STAT_CHANGING) | \
DIV_GPL(DIV_STAT_CHANGING))
/* CLK_SRC_RIGHTBUS */
#define MUX_GDR_SEL(x) ((x) & 0x1)
#define MUX_MPLL_USER_SEL_R(x) (((x) & 0x1) << 4)
/* CLK_MUX_STAT_RIGHTBUS */
#define GDR_SEL(x) ((x) & 0x7)
#define MPLL_USER_SEL_R(x) (((x) & 0x7) << 4)
#define MUX_STAT_RIGHTBUS_CHANGING (GDR_SEL(MUX_STAT_CHANGING) | \
MPLL_USER_SEL_R(MUX_STAT_CHANGING))
/* CLK_DIV_RIGHTBUS */
#define GPR_RATIO(x) ((x) & 0x7)
#define GDR_RATIO(x) (((x) & 0x7) << 4)
/* CLK_DIV_STAT_RIGHTBUS */
#define DIV_GDR(x) ((x) & 0x1)
#define DIV_GPR(x) ((x) & 0x1)
#define DIV_STAT_RIGHTBUS_CHANGING (DIV_GDR(DIV_STAT_CHANGING) | \
DIV_GPR(DIV_STAT_CHANGING))
/* CLK_SRC_PERIL0 */
#define UART0_SEL(x) ((x) & 0xf)
#define UART1_SEL(x) (((x) & 0xf) << 4)
#define UART2_SEL(x) (((x) & 0xf) << 8)
#define UART3_SEL(x) (((x) & 0xf) << 12)
#define UART4_SEL(x) (((x) & 0xf) << 16)
/* CLK_DIV_PERIL0 */
#define UART0_RATIO(x) ((x) & 0xf)
#define UART1_RATIO(x) (((x) & 0xf) << 4)
#define UART2_RATIO(x) (((x) & 0xf) << 8)
#define UART3_RATIO(x) (((x) & 0xf) << 12)
#define UART4_RATIO(x) (((x) & 0xf) << 16)
/* CLK_DIV_STAT_PERIL0 */
#define DIV_UART0(x) ((x) & 0x1)
#define DIV_UART1(x) (((x) & 0x1) << 4)
#define DIV_UART2(x) (((x) & 0x1) << 8)
#define DIV_UART3(x) (((x) & 0x1) << 12)
#define DIV_UART4(x) (((x) & 0x1) << 16)
#define DIV_STAT_PERIL0_CHANGING (DIV_UART4(DIV_STAT_CHANGING) | \
DIV_UART3(DIV_STAT_CHANGING) | \
DIV_UART2(DIV_STAT_CHANGING) | \
DIV_UART1(DIV_STAT_CHANGING) | \
DIV_UART0(DIV_STAT_CHANGING))
/* CLK_SRC_FSYS */
#define MMC1_SEL(x) (((x) & 0xf) << 4)
#define MMC2_SEL(x) (((x) & 0xf) << 8)
#define MMC3_SEL(x) (((x) & 0xf) << 12)
#define MMC4_SEL(x) (((x) & 0xf) << 16)
#define MIPIHSI_SEL(x) (((x) & 0x1) << 24)
/* CLK_DIV_FSYS0 */
#define MIPIHSI_RATIO(x) (((x) & 0xf) << 20)
/* CLK_DIV_STAT_FSYS0 */
#define DIV_MIPIHSI(x) (((x) & 0x1) << 20)
#define DIV_STAT_FSYS0_CHANGING (DIV_MIPIHSI(DIV_STAT_CHANGING))
/* CLK_DIV_FSYS1 */
#define MMC0_RATIO(x) ((x) & 0xf)
#define MMC0_PRE_RATIO(x) (((x) & 0xff) << 8)
#define MMC1_RATIO(x) (((x) & 0xf) << 16)
#define MMC1_PRE_RATIO(x) (((x) & 0xff) << 24)
/* CLK_DIV_STAT_FSYS1 */
#define DIV_MMC0(x) ((x) & 1)
#define DIV_MMC0_PRE(x) (((x) & 1) << 8)
#define DIV_MMC1(x) (((x) & 1) << 16)
#define DIV_MMC1_PRE(x) (((x) & 1) << 24)
#define DIV_STAT_FSYS1_CHANGING (DIV_MMC0(DIV_STAT_CHANGING) | \
DIV_MMC0_PRE(DIV_STAT_CHANGING) | \
DIV_MMC1(DIV_STAT_CHANGING) | \
DIV_MMC1_PRE(DIV_STAT_CHANGING))
/* CLK_DIV_FSYS2 */
#define MMC2_RATIO(x) ((x) & 0xf)
#define MMC2_PRE_RATIO(x) (((x) & 0xff) << 8)
#define MMC3_RATIO(x) (((x) & 0xf) << 16)
#define MMC3_PRE_RATIO(x) (((x) & 0xff) << 24)
/* CLK_DIV_STAT_FSYS2 */
#define DIV_MMC2(x) ((x) & 0x1)
#define DIV_MMC2_PRE(x) (((x) & 0x1) << 8)
#define DIV_MMC3(x) (((x) & 0x1) << 16)
#define DIV_MMC3_PRE(x) (((x) & 0x1) << 24)
#define DIV_STAT_FSYS2_CHANGING (DIV_MMC2(DIV_STAT_CHANGING) | \
DIV_MMC2_PRE(DIV_STAT_CHANGING) | \
DIV_MMC3(DIV_STAT_CHANGING) | \
DIV_MMC3_PRE(DIV_STAT_CHANGING))
/* CLK_DIV_FSYS3 */
#define MMC4_RATIO(x) ((x) & 0x7)
#define MMC4_PRE_RATIO(x) (((x) & 0xff) << 8)
/* CLK_DIV_STAT_FSYS3 */
#define DIV_MMC4(x) ((x) & 0x1)
#define DIV_MMC4_PRE(x) (((x) & 0x1) << 8)
#define DIV_STAT_FSYS3_CHANGING (DIV_MMC4(DIV_STAT_CHANGING) | \
DIV_MMC4_PRE(DIV_STAT_CHANGING))
/* DMC */
#ifdef CONFIG_CLK_800_330_165
#define DRAM_CLK_330
#endif
#ifdef CONFIG_CLK_1000_200_200
#define DRAM_CLK_200
#endif
#ifdef CONFIG_CLK_1000_330_165
#define DRAM_CLK_330
#endif
#ifdef CONFIG_CLK_1000_400_200
#define DRAM_CLK_400
#endif
/* Bus Configuration Register Address */
#define ASYNC_CONFIG 0x10010350
#define DIRECT_CMD_NOP 0x07000000
#define DIRECT_CMD_ZQ 0x0a000000
#define DIRECT_CMD_CHIP1_SHIFT (1 << 20)
#define MEM_TIMINGS_MSR_COUNT 4
#define CTRL_START (1 << 0)
#define CTRL_DLL_ON (1 << 1)
#define AREF_EN (1 << 5)
#define DRV_TYPE (1 << 6)
struct mem_timings {
unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
unsigned timingref;
unsigned timingrow;
unsigned timingdata;
unsigned timingpower;
unsigned zqcontrol;
unsigned control0;
unsigned control1;
unsigned control2;
unsigned concontrol;
unsigned prechconfig;
unsigned memcontrol;
unsigned memconfig0;
unsigned memconfig1;
unsigned dll_resync;
unsigned dll_on;
};
/* MIU */
/* MIU Config Register Offsets*/
#define APB_SFR_INTERLEAVE_CONF_OFFSET 0x400
#define APB_SFR_ARBRITATION_CONF_OFFSET 0xC00
#define ABP_SFR_SLV_ADDRMAP_CONF_OFFSET 0x800
#define ABP_SFR_INTERLEAVE_ADDRMAP_START_OFFSET 0x808
#define ABP_SFR_INTERLEAVE_ADDRMAP_END_OFFSET 0x810
#define ABP_SFR_SLV0_SINGLE_ADDRMAP_START_OFFSET 0x818
#define ABP_SFR_SLV0_SINGLE_ADDRMAP_END_OFFSET 0x820
#define ABP_SFR_SLV1_SINGLE_ADDRMAP_START_OFFSET 0x828
#define ABP_SFR_SLV1_SINGLE_ADDRMAP_END_OFFSET 0x830
#if (defined CONFIG_ORIGEN) || (defined CONFIG_ITOP4412)
/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */
#define APB_SFR_INTERLEAVE_CONF_VAL 0x20001507
#define APB_SFR_ARBRITATION_CONF_VAL 0x00000001
#endif
#define INTERLEAVE_ADDR_MAP_START_ADDR 0x40000000
#define INTERLEAVE_ADDR_MAP_END_ADDR 0xbfffffff
#define INTERLEAVE_ADDR_MAP_EN 0x00000001
#ifdef CONFIG_MIU_1BIT_INTERLEAVED
/* Interleave_bit0: 0xC*/
#define APB_SFR_INTERLEAVE_CONF_VAL 0x0000000c
#endif
#ifdef CONFIG_MIU_2BIT_INTERLEAVED
/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0xc */
#define APB_SFR_INTERLEAVE_CONF_VAL 0x2000150c
#endif
#define SLAVE0_SINGLE_ADDR_MAP_START_ADDR 0x40000000
#define SLAVE0_SINGLE_ADDR_MAP_END_ADDR 0x7fffffff
#define SLAVE1_SINGLE_ADDR_MAP_START_ADDR 0x80000000
#define SLAVE1_SINGLE_ADDR_MAP_END_ADDR 0xbfffffff
/* Enable SME0 and SME1*/
#define APB_SFR_SLV_ADDR_MAP_CONF_VAL 0x00000006
#define FORCE_DLL_RESYNC 3
#define DLL_CONTROL_ON 1
#define DIRECT_CMD1 0x00020000
#define DIRECT_CMD2 0x00030000
#define DIRECT_CMD3 0x00010002
#define DIRECT_CMD4 0x00000328
#define CTRL_ZQ_MODE_NOTERM (0x1 << 0)
#define CTRL_ZQ_START (0x1 << 1)
#define CTRL_ZQ_DIV (0 << 4)
#define CTRL_ZQ_MODE_DDS (0x7 << 8)
#define CTRL_ZQ_MODE_TERM (0x2 << 11)
#define CTRL_ZQ_FORCE_IMPN (0x5 << 14)
#define CTRL_ZQ_FORCE_IMPP (0x6 << 17)
#define CTRL_DCC (0xE38 << 20)
#define ZQ_CONTROL_VAL (CTRL_ZQ_MODE_NOTERM | CTRL_ZQ_START\
| CTRL_ZQ_DIV | CTRL_ZQ_MODE_DDS\
| CTRL_ZQ_MODE_TERM | CTRL_ZQ_FORCE_IMPN\
| CTRL_ZQ_FORCE_IMPP | CTRL_DCC)
#define ASYNC (0 << 0)
#define CLK_RATIO (1 << 1)
#define DIV_PIPE (1 << 3)
#define AWR_ON (1 << 4)
#define AREF_DISABLE (0 << 5)
#define DRV_TYPE_DISABLE (0 << 6)
#define CHIP0_NOT_EMPTY (0 << 8)
#define CHIP1_NOT_EMPTY (0 << 9)
#define DQ_SWAP_DISABLE (0 << 10)
#define QOS_FAST_DISABLE (0 << 11)
#define RD_FETCH (0x3 << 12)
#define TIMEOUT_LEVEL0 (0xFFF << 16)
#define CONCONTROL_VAL (ASYNC | CLK_RATIO | DIV_PIPE | AWR_ON\
| AREF_DISABLE | DRV_TYPE_DISABLE\
| CHIP0_NOT_EMPTY | CHIP1_NOT_EMPTY\
| DQ_SWAP_DISABLE | QOS_FAST_DISABLE\
| RD_FETCH | TIMEOUT_LEVEL0)
#define CLK_STOP_DISABLE (0 << 1)
#define DPWRDN_DISABLE (0 << 2)
#define DPWRDN_TYPE (0 << 3)
#define TP_DISABLE (0 << 4)
#define DSREF_DIABLE (0 << 5)
#define ADD_LAT_PALL (1 << 6)
#define MEM_TYPE_DDR3 (0x6 << 8)
#define MEM_WIDTH_32 (0x2 << 12)
#define NUM_CHIP_2 (0 << 16)
#define BL_8 (0x3 << 20)
#define MEMCONTROL_VAL (CLK_STOP_DISABLE | DPWRDN_DISABLE\
| DPWRDN_TYPE | TP_DISABLE | DSREF_DIABLE\
| ADD_LAT_PALL | MEM_TYPE_DDR3 | MEM_WIDTH_32\
| NUM_CHIP_2 | BL_8)
#define CHIP_BANK_8 (0x3 << 0)
#define CHIP_ROW_14 (0x3 << 4)
#define CHIP_COL_10 (0x3 << 8)
#define CHIP_MAP_INTERLEAVED (1 << 12)
#define CHIP_MASK (0xC0 << 16)
#ifdef CONFIG_MIU_LINEAR
#define CHIP0_BASE (0x40 << 24)
#define CHIP1_BASE (0x60 << 24)
#else
#define CHIP0_BASE (0x40 << 24)
#define CHIP1_BASE (0x80 << 24)
#endif
#define MEMCONFIG0_VAL (CHIP_BANK_8 | CHIP_ROW_14 | CHIP_COL_10\
| CHIP_MAP_INTERLEAVED | CHIP_MASK | CHIP0_BASE)
#define MEMCONFIG1_VAL (CHIP_BANK_8 | CHIP_ROW_14 | CHIP_COL_10\
| CHIP_MAP_INTERLEAVED | CHIP_MASK | CHIP1_BASE)
#define TP_CNT (0xff << 24)
#define PRECHCONFIG TP_CNT
#define CTRL_OFF (0 << 0)
#define CTRL_DLL_OFF (0 << 1)
#define CTRL_HALF (0 << 2)
#define CTRL_DFDQS (1 << 3)
#define DQS_DELAY (0 << 4)
#define CTRL_START_POINT (0x10 << 8)
#define CTRL_INC (0x10 << 16)
#define CTRL_FORCE (0x71 << 24)
#define CONTROL0_VAL (CTRL_OFF | CTRL_DLL_OFF | CTRL_HALF\
| CTRL_DFDQS | DQS_DELAY | CTRL_START_POINT\
| CTRL_INC | CTRL_FORCE)
#define CTRL_SHIFTC (0x6 << 0)
#define CTRL_REF (8 << 4)
#define CTRL_SHGATE (1 << 29)
#define TERM_READ_EN (1 << 30)
#define TERM_WRITE_EN (1 << 31)
#define CONTROL1_VAL (CTRL_SHIFTC | CTRL_REF | CTRL_SHGATE\
| TERM_READ_EN | TERM_WRITE_EN)
#define CONTROL2_VAL 0x00000000
#ifdef CONFIG_ITOP4412
#define TIMINGREF_VAL 0x000000BB
#define TIMINGROW_VAL 0x4046654f
#define TIMINGDATA_VAL 0x46400506
#define TIMINGPOWER_VAL 0x52000A3C
#else
#define TIMINGREF_VAL 0x000000BC
#ifdef DRAM_CLK_330
#define TIMINGROW_VAL 0x3545548d
#define TIMINGDATA_VAL 0x45430506
#define TIMINGPOWER_VAL 0x4439033c
#endif
#ifdef DRAM_CLK_400
#define TIMINGROW_VAL 0x45430506
#define TIMINGDATA_VAL 0x56500506
#define TIMINGPOWER_VAL 0x5444033d
#endif
#endif
#ifdef CONFIG_BOARD_TYPES
extern void sdelay(unsigned long);
#endif
#endif
3.修改时钟初始化clock_init_exynos4.c
添加的代码较多，此次直接贴出所有的，详情如下：
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/clk.h>
#include <asm/arch/clock.h>
#include "common_setup.h"
#ifdef CONFIG_ITOP4412
# include "itop4412_setup.h"
#else
# include "exynos4_setup.h"
#endif
/*
* system_clock_init: Initialize core clock and bus clock.
* void system_clock_init(void)
*/
#ifndef CONFIG_ITOP4412
void system_clock_init(void)
{
struct exynos4_clock *clk =
(struct exynos4_clock *)samsung_get_base_clock();
writel(CLK_SRC_CPU_VAL, &clk->src_cpu);
writel(VPLL_CON1_VAL, &clk->vpll_con1);
writel(VPLL_CON0_VAL, &clk->vpll_con0);
sdelay(0x30000);
}
#else
/**
* freq (ARMCLK) = 1400 MHz at 1.3 V
* freq (ACLK_COREM0) = 350 MHz at 1.3V
* freq (ACLK_COREM1) = 188 MHz at 1.3 V
* freq (PERIPHCLK) = 1400 MHz at 1.3 V
* freq (ACLK_200) = 160 MHz at 1.0 V
* freq (ACLK_100) = 100 MHz at 1.0 V
* freq (ACLK_160) = 160 MHz at 1.0 V
* freq (ACLK_133) = 133 MHz at 1.0 V
* freq (SCLK_ONENAND) = 160 MHz at 1.0 V
*/
void system_clock_init(void)
{
unsigned int set, clr, clr_src_cpu, clr_pll_con0, clr_src_dmc;
struct exynos4x12_clock *clk = (struct exynos4x12_clock *)
samsung_get_base_clock();
/************************************************************
* Step 1:
*
* Set PDIV, MDIV, and SDIV values (Refer to (A, M, E, V)
* Change other PLL control values
* PCLK_DBG = ATCLK / (PCLK_DBG_RATIO + 1) = 100 MHz (1)
* SCLKapll = MOUTapll / (APLL_RATIO + 1) = 500 MHz (1)
* ARMCLK = DOUTcore / (CORE2_RATIO + 1) = 1000 MHz (0)
*/
/** CLK_DIV_CPU0 */
clr = CORE_RATIO(7) | COREM0_RATIO(7) | COREM1_RATIO(7) |
PERIPH_RATIO(7) | ATB_RATIO(7) | PCLK_DBG_RATIO(7) |
APLL_RATIO(7) | CORE2_RATIO(7);
set = CORE_RATIO(0) | COREM0_RATIO(3) | COREM1_RATIO(7) |
PERIPH_RATIO(0) | ATB_RATIO(4) | PCLK_DBG_RATIO(1) |
APLL_RATIO(1) | CORE2_RATIO(0);
clrsetbits_le32(&clk->div_cpu0, clr, set);
/* Wait for divider ready status */
while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING)
continue;
/**
* Set dividers for MOUThpm = 1000 MHz (MOUTapll)
*
* DOUTcopy = MOUThpm / (COPY_RATIO + 1) = 200 MHz (4)
* SCLK_HPM = DOUTcopy / (HPM_RATIO + 1) = 200 MHz (0)
* ACLK_CORES = ARMCLK / (CORES_RATIO + 1) = 1000 MHz (0)
*/
/** CLK_DIV_CPU1 */
clr = COPY_RATIO(7) | HPM_RATIO(7) | CORES_RATIO(7);
set = COPY_RATIO(4) | HPM_RATIO(0) | CORES_RATIO(0);
clrsetbits_le32(&clk->div_cpu1, clr, set);
/* Wait for divider ready status */
while (readl(&clk->div_stat_cpu1) & DIV_STAT_CPU1_CHANGING)
continue;
/**
* Set dividers for -->
* MOUTdmc = 800 MHz
* MOUTdphy = 800 MHz
*
* SCLK_DMC = MOUTdmc / (DMC_RATIO + 1) = 400 MHz (1)
* ACLK_DMCD = SCLK_DMC / (DMCD_RATIO + 1) = 200 MHz (1)
* ACLK_DMCP = ACLK_DMCD / (DMCP_RATIO + 1) = 100 MHz (1)
*/
/** CLK_DIV_DMC0 */
clr = ACP_RATIO(7) | ACP_PCLK_RATIO(7) | DPHY_RATIO(7) |
DMC_RATIO(7) | DMCD_RATIO(7) | DMCP_RATIO(7);
set = ACP_RATIO(3) | ACP_PCLK_RATIO(1) | DPHY_RATIO(1) |
DMC_RATIO(1) | DMCD_RATIO(1) | DMCP_RATIO(1);
clrsetbits_le32(&clk->div_dmc0, clr, set);
/* Wait for divider ready status */
while (readl(&clk->div_stat_dmc0) & DIV_STAT_DMC0_CHANGING)
continue;
/**
* For:
* MOUTg2d = 800 MHz
* MOUTc2c = 800 Mhz
* MOUTpwi = 24 MHz
* ACLK_C2C = SCLK_C2C / (C2C_ACLK_RATIO + 1) = 200 MHz (1)
* DVSEM_RATIO : It decides frequency for PWM frame time slot in DVS emulation mode.
* DPM_RATIO : It decides frequency of DPM channel clock.
*/
/** CLK_DIV_DMC1 */
clr = G2D_ACP_RATIO(15) | C2C_RATIO(7) | PWI_RATIO(15) |
C2C_ACLK_RATIO(7) | DVSEM_RATIO(127) | DPM_RATIO(127);
set = G2D_ACP_RATIO(3) | C2C_RATIO(1) | PWI_RATIO(0) |
C2C_ACLK_RATIO(1) | DVSEM_RATIO(1) | DPM_RATIO(1);
clrsetbits_le32(&clk->div_dmc1, clr, set);
/* Wait for divider ready status */
while (readl(&clk->div_stat_dmc1) & DIV_STAT_DMC1_CHANGING)
continue;
/**
* MOUTmpll = 800 MHz
* MOUTvpll = 54 MHz
*
* ACLK_200 = MOUTACLK_200 / (ACLK_200_RATIO + 1) = 200 MHz (3)
* ONENAND = MOUTONENAND_1 / (ONENAND_RATIO + 1) = 160 MHz (0)
* ACLK_266_GPS = MOUTACLK_266_GPS / (ACLK_266_GPS_RATIO + 1) = 266 MHz (2)
* ACLK_400_MCUISP = MOUTACLK_400_MCUISP / (ACLK_400_MCUISP_RATIO + 1) = 400 MHz (1)
*/
/** CLK_DIV_TOP */
clr = ACLK_200_RATIO(7) | ACLK_100_RATIO(15) | ACLK_160_RATIO(7) |
ACLK_133_RATIO(7) | ONENAND_RATIO(7) | ACLK_266_GPS_RATIO(7) | ACLK_400_MCUISP_RATIO(7);
set = ACLK_200_RATIO(3) | ACLK_100_RATIO(7) | ACLK_160_RATIO(4) |
ACLK_133_RATIO(5) | ONENAND_RATIO(0) | ACLK_266_GPS_RATIO(2) | ACLK_400_MCUISP_RATIO(1);
clrsetbits_le32(&clk->div_top, clr, set);
/* Wait for divider ready status */
while (readl(&clk->div_stat_top) & DIV_STAT_TOP_CHANGING)
continue;
/**
* ACLK_GDL = MOUTGDL / (GDL_RATIO + 1) = 200 MHz (3)
* ACLK_GPL = MOUTGPL / (GPL_RATIO + 1) = 100 MHz (1)
*/
/** CLK_DIV_LEFTBUS */
clr = GDL_RATIO(7) | GPL_RATIO(7);
set = GDL_RATIO(3) | GPL_RATIO(1);
clrsetbits_le32(&clk->div_leftbus, clr, set);
/* Wait for divider ready status */
while (readl(&clk->div_stat_leftbus) & DIV_STAT_LEFTBUS_CHANGING)
continue;
/**
* ACLK_GDR = MOUTGDR / (GDR_RATIO + 1) = 200 MHz (3)
* ACLK_GPR = MOUTGPR / (GPR_RATIO + 1) = 100 MHz (1)
*/
/** CLK_DIV_RIGHTBUS */
clr = GPR_RATIO(7) | GDR_RATIO(7);
set = GPR_RATIO(3) | GDR_RATIO(1);
clrsetbits_le32(&clk->div_rightbus, clr, set);
/* Wait for divider ready status */
while (readl(&clk->div_stat_rightbus) & DIV_STAT_RIGHTBUS_CHANGING)
continue;
/**
* MOUTUART[1-4] = 800 Mhz (MPLL)
*
* SCLK_UART0 = MOUTUART0 / (UART0_RATIO + 1) = 100 MHz (7)
* SCLK_UART1 = MOUTUART1 / (UART1_RATIO + 1) = 100 MHz (7)
* SCLK_UART2 = MOUTUART2 / (UART2_RATIO + 1) = 100 MHz (7)
* SCLK_UART3 = MOUTUART3 / (UART3_RATIO + 1) = 100 MHz (7)
* SCLK_UART4 = MOUTUART4 / (UART4_RATIO + 1) = 100 MHz (7)
*/
/** CLK_DIV_PERIL0 */
clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) |
UART3_RATIO(15) | UART4_RATIO(15);
set = UART0_RATIO(7) | UART1_RATIO(7) | UART2_RATIO(7) |
UART3_RATIO(7) | UART4_RATIO(7);
clrsetbits_le32(&clk->div_peril0, clr, set);
/* Wait for divider ready status */
while (readl(&clk->div_stat_peril0) & DIV_STAT_PERIL0_CHANGING)
continue;
/**
* For MOUTMMC0-3 = 800 MHz (MPLL)
*
* SCLK_MIPIHSI = MOUTMIPIHSI / (MIPIHSI_RATIO + 1) = 200 MHz (3)
*/
/* CLK_DIV_FSYS0 */
clr = MIPIHSI_RATIO(15);
set = MIPIHSI_RATIO(3);
clrsetbits_le32(&clk->div_fsys0, clr, set);
/* Wait for divider ready status */
while (readl(&clk->div_stat_fsys0) & DIV_STAT_FSYS0_CHANGING)
continue;
/**
* For MOUTMMC0-3 = 800 MHz (MPLL)
*
* DOUTMMC0 = MOUTMMC0 / (MMC0_RATIO + 1) = 100 MHz (7)
* SCLK_MMC0 = DOUTMMC0 / (MMC0_PRE_RATIO + 1) = 50 MHz (1)
* DOUTMMC1 = MOUTMMC1 / (MMC1_RATIO + 1) = 100 MHz (7)
* SCLK_MMC1 = DOUTMMC1 / (MMC1_PRE_RATIO + 1) = 50 MHz (1)
*/
/* CLK_DIV_FSYS1 */
clr = MMC0_RATIO(15) | MMC0_PRE_RATIO(255) | MMC1_RATIO(15) |
MMC1_PRE_RATIO(255);
set = MMC0_RATIO(7) | MMC0_PRE_RATIO(1) | MMC1_RATIO(7) |
MMC1_PRE_RATIO(1);
clrsetbits_le32(&clk->div_fsys1, clr, set);
/* Wait for divider ready status */
while (readl(&clk->div_stat_fsys1) & DIV_STAT_FSYS1_CHANGING)
continue;
/**
* For MOUTmmc0-3 = 800 MHz (MPLL)
*
* DOUTmmc3 = MOUTmmc3 / (MMC2_RATIO + 1) = 100 MHz (7)
* sclk_mmc3 = DOUTmmc3 / (MMC2_PRE_RATIO + 1) = 50 MHz (1)
* DOUTmmc2 = MOUTmmc2 / (MMC3_RATIO + 1) = 100 MHz (7)
* sclk_mmc2 = DOUTmmc2 / (MMC3_PRE_RATIO + 1) = 50 MHz (1)
*/
/* CLK_DIV_FSYS2 */
clr = MMC2_RATIO(15) | MMC2_PRE_RATIO(255) | MMC3_RATIO(15) |
MMC3_PRE_RATIO(255);
set = MMC2_RATIO(7) | MMC2_PRE_RATIO(1) | MMC3_RATIO(7) |
MMC3_PRE_RATIO(1);
clrsetbits_le32(&clk->div_fsys2, clr, set);
/* Wait for divider ready status */
while (readl(&clk->div_stat_fsys2) & DIV_STAT_FSYS2_CHANGING)
continue;
/**
* For MOUTmmc4 = 800 MHz (MPLL)
*
* DOUTmmc4 = MOUTmmc4 / (MMC4_RATIO + 1) = 100 MHz (7)
* sclk_mmc4 = DOUTmmc4 / (MMC4_PRE_RATIO + 1) = 50 MHz (1)
*/
/* CLK_DIV_FSYS3 */
clr = MMC4_RATIO(15) | MMC4_PRE_RATIO(255);
set = MMC4_RATIO(7) | MMC4_PRE_RATIO(1);
clrsetbits_le32(&clk->div_fsys3, clr, set);
/* Wait for divider ready status */
while (readl(&clk->div_stat_fsys3) & DIV_STAT_FSYS3_CHANGING)
continue;
/************************************************************
* Step 2:
*
* Set K, AFC, MRR, MFR values if necessary
* (Refer to (A, M, E, V)PLL_CON1 SFRs)
* Turn on a PLL (Refer to (A, M, E, V) PLL_CON0 SFRs)
************************************************************/
/* Set APLL to 1000MHz */
/** APLL_CON1 */
clr = AFC(31) | LOCK_CON_DLY(31) | LOCK_CON_IN(3) |
LOCK_CON_OUT(3) |FEED_EN(1)| AFC_ENB(1) |
DCC_ENB(1) | BYPASS(1) |RESV0(1) | RESV1(1);
set = AFC(0) | LOCK_CON_DLY(8) | LOCK_CON_IN(3) |
LOCK_CON_OUT(0) |FEED_EN(0)| AFC_ENB(0) |
DCC_ENB(1) | BYPASS(0) |RESV0(0) | RESV1(0);
clrsetbits_le32(&clk->apll_con1, clr, set);
/** APLL_CON0 */
clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1) | PLL_ENABLE(1);
set = SDIV(0) | PDIV(3) | MDIV(125) | FSEL(0) | PLL_ENABLE(1);
clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set);
/* Wait for PLL to be locked */
while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT))
continue;
/* Set MPLL to 800MHz */
/** MPLL_CON1 */
clr = AFC(31) | LOCK_CON_DLY(31) | LOCK_CON_IN(3) |
LOCK_CON_OUT(3) |FEED_EN(1)| AFC_ENB(1) |
DCC_ENB(1) | BYPASS(1) |RESV0(1) | RESV1(1);
set = AFC(0) | LOCK_CON_DLY(8) | LOCK_CON_IN(3) |
LOCK_CON_OUT(0) |FEED_EN(0)| AFC_ENB(0) |
DCC_ENB(1) | BYPASS(0) |RESV0(0) | RESV1(0);
clrsetbits_le32(&clk->mpll_con1, clr, set);
/** MPLL_CON0 */
clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1) | PLL_ENABLE(1);
set = SDIV(0) | PDIV(3) | MDIV(100) | FSEL(0) | PLL_ENABLE(1);
clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set);
/* Wait for PLL to be locked */
while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT))
continue;
/* Set EPLL to 192MHz */
/** EPLL_CON2 */
clr = ICP_BOOST(7) | EV_FSEL(1) | FVCO_EN(1) | EV_BYPASS(1) |
SSCG_EN(1) | EV_AFC_ENB(1) | EV_DCC_ENB(1) | EXTAFC(1);
set = ICP_BOOST(0) | EV_FSEL(1) | FVCO_EN(1) | EV_BYPASS(1) |
SSCG_EN(0) | EV_AFC_ENB(0) | EV_DCC_ENB(1) | EXTAFC(0);
clrsetbits_le32(&clk->epll_con2, clr, set);
/** EPLL_CON1 */
/* there is null */
/** EPLL_CON0 */
clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1) | PLL_ENABLE(1);
set = SDIV(2) | PDIV(2) | MDIV(64) | FSEL(0) | PLL_ENABLE(1);
clrsetbits_le32(&clk->epll_con0, clr_pll_con0, set);
/* Wait for PLL to be locked */
while (!(readl(&clk->epll_con0) & PLL_LOCKED_BIT))
continue;
/* Set VPLL to 54MHz */
/** VPLL_CON2 */
clr = ICP_BOOST(7) | EV_FSEL(1) | FVCO_EN(1) | EV_BYPASS(1) |
SSCG_EN(1) | EV_AFC_ENB(1) | EV_DCC_ENB(1) | EXTAFC(1);
set = ICP_BOOST(0) | EV_FSEL(1) | FVCO_EN(1) | EV_BYPASS(1) |
SSCG_EN(0) | EV_AFC_ENB(0) | EV_DCC_ENB(1) | EXTAFC(0);
clrsetbits_le32(&clk->vpll_con2, clr, set);
/** VPLL_CON1 */
/* there is null */
/** VPLL_CON0 */
clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1) | PLL_ENABLE(1);
set = SDIV(3) | PDIV(3) | MDIV(54) | FSEL(0) | PLL_ENABLE(1);
clrsetbits_le32(&clk->vpll_con0, clr_pll_con0, set);
/* Wait for PLL to be locked */
while (!(readl(&clk->vpll_con0) & PLL_LOCKED_BIT))
continue;
/************************************************************
*Step 3:
*
* Wait until the PLL is locked
************************************************************/
clr = PLL_LOCKTIME(65535);
/** APLL LOCKTIME 1000MHz */
set = PLL_LOCKTIME(PDIV(3) * 270);
clrsetbits_le32(&clk->apll_lock, clr, set);
/** MPLL LOCKTIME 800MHz */
set = PLL_LOCKTIME(PDIV(3) * 270);
clrsetbits_le32(&clk->mpll_lock, clr, set);
/** EPLL LOCKTIME 192MHz */
set = PLL_LOCKTIME(PDIV(2) * 270);
clrsetbits_le32(&clk->epll_lock, clr, set);
/** VPLL LOCKTIME 54MHz */
set = PLL_LOCKTIME(PDIV(3) * 270);
clrsetbits_le32(&clk->vpll_lock, clr, set);
/************************************************************
* Step 4:
*
* Select the PLL output clock instead of input reference clock,
* after PLL output clock is stabilized.
* MUX_APLL_SEL: FIN_PLL ; MOUTAPLLFOUT
* MUX_CORE_SEL: MOUTAPLL ; SCLKMPLL
* MUX_HPM_SEL: MOUTAPLL ; SCLKMPLL
* MUX_MPLL_USER_SEL_C: FINPLL ; FOUTMPLL
*/
/** CLK_SRC_CPU */
clr_src_cpu = MUX_APLL_SEL(1) | MUX_CORE_SEL(1) |
MUX_HPM_SEL(1) | MUX_MPLL_USER_SEL_C(1);
set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0) | MUX_HPM_SEL(0) |
MUX_MPLL_USER_SEL_C(1);
clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
/* Wait for mux change */
while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING)
continue;
/**
* Set CMU_DMC default clocks src to APLL
*
* Bit values: 0 ; 1
* MUX_C2C_SEL: SCLKMPLL ; SCLKAPLL
* MUX_PWI_SEL: 0110 (MPLL); 0111 (EPLL); 1000 (VPLL); 0(XXTI)
* MUX_G2D_ACP0_SEL: SCLKMPLL ; SCLKAPLL
* MUX_G2D_ACP1_SEL: SCLKEPLL ; SCLKVPLL
* MUX_G2D_ACP_SEL: OUT_ACP0 ; OUT_ACP1
*/
/** CLK_SRC_DMC */
clr_src_dmc = MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) |
MUX_DPHY_SEL(1) | MUX_MPLL_SEL(1) |
MUX_PWI_SEL(15) | MUX_G2D_ACP0_SEL(1) |
MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1);
set = MUX_C2C_SEL(0) | MUX_DMC_BUS_SEL(0) | MUX_DPHY_SEL(0) |
MUX_MPLL_SEL(1) | MUX_PWI_SEL(0) | MUX_G2D_ACP0_SEL(0) |
MUX_G2D_ACP1_SEL(0) | MUX_G2D_ACP_SEL(0);
clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set);
/* Wait for mux change */
while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING)
continue;
/**
* Set CMU_TOP default clocks src to APLL
*
* Bit values: 0 ; 1
* MUX_ONENAND_1_SEL MOUTONENAND ; SCLKVPLL
* MUX_ACLK_160_SEL SCLKMPLL ; SCLKAPLL
* MUX_ACLK_133_SEL SCLKMPLL ; SCLKAPLL
* MUX_ONENAND_SEL ACLK_133 ; ACLK_160
*/
/* CLK_SRC_TOP0 */
clr = MUX_ONENAND_1_SEL(1) | MUX_EPLL_SEL(1) | MUX_VPLL_SEL(1) |
MUX_ACLK_200_SEL(1) | MUX_ACLK_100_SEL(1) | MUX_ACLK_160_SEL(1) |
MUX_ACLK_133_SEL(1) | MUX_ONENAND_SEL(1);
set = MUX_ONENAND_1_SEL(0) | MUX_EPLL_SEL(1) | MUX_VPLL_SEL(1) |
MUX_ACLK_200_SEL(0) | MUX_ACLK_100_SEL(0) | MUX_ACLK_160_SEL(0) |
MUX_ACLK_133_SEL(0) | MUX_ONENAND_SEL(1);
clrsetbits_le32(&clk->src_top0, clr, set);
/* Wait for mux change */
while (readl(&clk->mux_stat_top0) & MUX_STAT_TOP0_CHANGING)
continue;
/**
* Bit values: 0 ; 1
* MUX_ACLK_266_GPS_SEL SCLKMPLL_USER_T ; SCLKAPLL
* MUX_ACLK_400_MCUISP_SEL SCLKMPLL_USER_T ; SCLKAPLL
* MUX_MPLL_USER_SEL_T FINPLL ; SCLKMPLLL
* MUX_ACLK_266_GPS_SUB_SEL FINPLL ; DIVOUT_ACLK_266_GPS
* MUX_ACLK_200_SUB_SEL FINPLL ; DIVOUT_ACLK_200
* MUX_ACLK_400_MCUISP_SUB_SEL FINPLL
*/
/* CLK_SRC_TOP1 */
clr = MUX_ACLK_266_GPS_SEL(1) | MUX_ACLK_400_MCUISP_SEL(1) |
MUX_MPLL_USER_SEL_T(1) | MUX_ACLK_266_GPS_SUB_SEL(1) |
MUX_ACLK_200_SUB_SEL(1) | MUX_ACLK_400_MCUISP_SUB_SEL(1);
set = MUX_ACLK_266_GPS_SEL(0) | MUX_ACLK_400_MCUISP_SEL(0) |
MUX_MPLL_USER_SEL_T(1) | MUX_ACLK_266_GPS_SUB_SEL(1) |
MUX_ACLK_200_SUB_SEL(1) | MUX_ACLK_400_MCUISP_SUB_SEL(1);
clrsetbits_le32(&clk->src_top1, clr, set);
/* Wait for mux change */
while (readl(&clk->mux_stat_top1) & MUX_STAT_TOP1_CHANGING)
continue;
/* CLK_SRC_LEFTBUS */
clr = MUX_GDL_SEL(1) | MUX_MPLL_USER_SEL_L(1);
set = MUX_GDL_SEL(0) | MUX_MPLL_USER_SEL_L(1);
clrsetbits_le32(&clk->src_leftbus, clr, set);
/* Wait for mux change */
while (readl(&clk->mux_stat_leftbus) & MUX_STAT_LEFTBUS_CHANGING)
continue;
/* CLK_SRC_RIGHTBUS */
clr = MUX_GDR_SEL(1) | MUX_MPLL_USER_SEL_R(1);
set = MUX_GDR_SEL(0) | MUX_MPLL_USER_SEL_R(1);
clrsetbits_le32(&clk->src_rightbus, clr, set);
/* Wait for mux change */
while (readl(&clk->mux_stat_rightbus) & MUX_STAT_RIGHTBUS_CHANGING)
continue;
/** CLK_SRC_PERIL0 */
clr = UART0_SEL(15) | UART1_SEL(15) | UART2_SEL(15) |
UART3_SEL(15) | UART4_SEL(15);
set = UART0_SEL(6) | UART1_SEL(6) | UART2_SEL(6) |
UART3_SEL(6) | UART4_SEL(6);
clrsetbits_le32(&clk->src_peril0, clr, set);
/** CLK_SRC_FSYS */
clr = MMC1_SEL(15) | MMC2_SEL(15) | MMC3_SEL(15) |
MMC4_SEL(15) | MIPIHSI_SEL(1);
set = MMC1_SEL(6) | MMC2_SEL(6) | MMC3_SEL(6) |
MMC4_SEL(6) | MIPIHSI_SEL(0);
clrsetbits_le32(&clk->src_fsys, clr, set);
}
#endif
4. 修改内存初始化dmc_init_exynos4.c
此文件修改较少，直接贴出diff内容。如下：
diff --git a/arch/arm/mach-exynos/dmc_init_exynos4.c b/arch/arm/mach-exynos/dmc_init_exynos4.c
index ecddc72..8e9c64e 100644
--- a/arch/arm/mach-exynos/dmc_init_exynos4.c
+++ b/arch/arm/mach-exynos/dmc_init_exynos4.c
@@ -26,7 +26,12 @@
#include <config.h>
#include <asm/arch/dmc.h>
#include "common_setup.h"
-#include "exynos4_setup.h"
+
+#ifdef CONFIG_ITOP4412
+# include "itop4412_setup.h"
+#else
+# include "exynos4_setup.h"
+#endif
struct mem_timings mem = {
.direct_cmd_msr = {
@@ -175,7 +180,7 @@ void mem_ctrl_init(int reset)
* 0: full_sync
*/
writel(1, ASYNC_CONFIG);
-#ifdef CONFIG_ORIGEN
+#ifdef CONFIG_ITOP4412
/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */
writel(APB_SFR_INTERLEAVE_CONF_VAL, EXYNOS4_MIU_BASE +
APB_SFR_INTERLEAVE_CONF_OFFSET);
5. 修改clock.c
clock.c文件中关于mmc和lcd部分的结构体用错了，应该使用struct exynos4x12_clock，而非struct exynos4_clock，修改如下：
diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c
index 3d31f9d..7ab86d6 100644
--- a/arch/arm/mach-exynos/clock.c
+++ b/arch/arm/mach-exynos/clock.c
@@ -783,8 +783,13 @@ static unsigned long exynos4x12_get_uart_clk(int dev_index)
static unsigned long exynos4_get_mmc_clk(int dev_index)
{
+#ifdef CONFIG_ITOP4412
+ struct exynos4x12_clock *clk =
+ (struct exynos4x12_clock *)samsung_get_base_clock();
+#else
struct exynos4_clock *clk =
(struct exynos4_clock *)samsung_get_base_clock();
+#endif
unsigned long uclk, sclk;
unsigned int sel, ratio, pre_ratio;
int shift = 0;
@@ -833,10 +838,14 @@ static unsigned long exynos4_get_mmc_clk(int dev_index)
/* exynos4: set the mmc clock */
static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
{
+#ifdef CONFIG_ITOP4412
+ struct exynos4x12_clock *clk =
+ (struct exynos4x12_clock *)samsung_get_base_clock();
+#else
struct exynos4_clock *clk =
(struct exynos4_clock *)samsung_get_base_clock();
+#endif
unsigned int addr, clear_bit, set_bit;
-
/*
* CLK_DIV_FSYS1
* MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
@@ -912,8 +921,13 @@ static void exynos5420_set_mmc_clk(int dev_index, unsigned int div)
/* get_lcd_clk: return lcd clock frequency */
static unsigned long exynos4_get_lcd_clk(void)
{
+#ifdef CONFIG_ITOP4412
+ struct exynos4x12_clock *clk =
+ (struct exynos4x12_clock *)samsung_get_base_clock();
+#else
struct exynos4_clock *clk =
(struct exynos4_clock *)samsung_get_base_clock();
+#endif
unsigned long pclk, sclk;
unsigned int sel;
unsigned int ratio;
@@ -922,7 +936,11 @@ static unsigned long exynos4_get_lcd_clk(void)
* CLK_SRC_LCD0
* FIMD0_SEL [3:0]
*/
+#ifdef CONFIG_ITOP4412
+ sel = readl(&clk->src_lcd);
+#else
sel = readl(&clk->src_lcd0);
+#endif
sel = sel & 0xf;
/*
@@ -943,7 +961,11 @@ static unsigned long exynos4_get_lcd_clk(void)
* CLK_DIV_LCD0
* FIMD0_RATIO [3:0]
*/
+#ifdef CONFIG_ITOP4412
+ ratio = readl(&clk->div_lcd);
+#else
ratio = readl(&clk->div_lcd0);
+#endif
ratio = ratio & 0xf;
pclk = sclk / (ratio + 1);
@@ -1063,8 +1085,13 @@ static unsigned long exynos5800_get_lcd_clk(void)
void exynos4_set_lcd_clk(void)
{
+#ifdef CONFIG_ITOP4412
+ struct exynos4x12_clock *clk =
+ (struct exynos4x12_clock *)samsung_get_base_clock();
+#else
struct exynos4_clock *clk =
(struct exynos4_clock *)samsung_get_base_clock();
+#endif
/*
* CLK_GATE_BLOCK
@@ -1086,7 +1113,11 @@ void exynos4_set_lcd_clk(void)
* MIPI0_SEL [12:15]
* set lcd0 src clock 0x6: SCLK_MPLL
*/
+#ifdef CONFIG_ITOP4412
+ clrsetbits_le32(&clk->src_lcd, 0xf, 0x6);
+#else
clrsetbits_le32(&clk->src_lcd0, 0xf, 0x6);
+#endif
/*
* CLK_GATE_IP_LCD0
@@ -1098,7 +1129,11 @@ void exynos4_set_lcd_clk(void)
* CLK_PPMULCD0 [5]
* Gating all clocks for FIMD0
*/
+#ifdef CONFIG_ITOP4412
+ setbits_le32(&clk->gate_ip_lcd, 1 << 0);
+#else
setbits_le32(&clk->gate_ip_lcd0, 1 << 0);
+#endif
/*
* CLK_DIV_LCD0
@@ -1110,7 +1145,11 @@ void exynos4_set_lcd_clk(void)
* MIPI0_PRE_RATIO [23:20]
* set fimd ratio
*/
+#ifdef CONFIG_ITOP4412
+ clrsetbits_le32(&clk->div_lcd, 0xf, 0x1);
+#else
clrsetbits_le32(&clk->div_lcd0, 0xf, 0x1);
+#endif
}
void exynos5_set_lcd_clk(void)
6. 修改修改lowlevel_init.c
由于itop-4412开发板用的串口是串口2，需要改一下；还有就是tzpc的初始化，现在学习阶段暂时不关心tzpc，不需要调用。修改如下：
diff --git a/arch/arm/mach-exynos/lowlevel_init.c b/arch/arm/mach-exynos/lowlevel_init.c
index 1e090fd..c9c76b6 100644
--- a/arch/arm/mach-exynos/lowlevel_init.c
+++ b/arch/arm/mach-exynos/lowlevel_init.c
@@ -218,12 +218,20 @@ int do_lowlevel_init(void)
#ifdef CONFIG_DEBUG_UART
#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL_SUPPORT)) || \
!defined(CONFIG_SPL_BUILD)
+
+#ifdef CONFIG_ITOP4412
+ exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE);
+#else
exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
+#endif
debug_uart_init();
#endif
#endif
mem_ctrl_init(actions & DO_MEM_RESET);
+
+#ifndef CONFIG_ITOP4412
tzpc_init();
+#endif
}
return actions & DO_WAKEUP;
7.修改电源相关代码
- 修改power.h
根据三星原厂exynos4412芯片资料的8.8 Register Description ，添加exynos4x12_power结构体
diff --git a/arch/arm/mach-exynos/include/mach/power.h b/arch/arm/mach-exynos/include/mach/power.h
index 88f70d9..27ce69f 100644
--- a/arch/arm/mach-exynos/include/mach/power.h
+++ b/arch/arm/mach-exynos/include/mach/power.h
@@ -210,6 +210,214 @@ struct exynos4_power {
unsigned int gps_alive_option;
};
+struct exynos4x12_power {
+ unsigned int om_stat;
+ unsigned char res1[0xc];
+ unsigned int rtc_clko_sel;
+ unsigned int gnss_rtc_out_ctrl;
+ unsigned int lpi_denial_mask0;
+ unsigned int lpi_denial_mask1;
+ unsigned int lpi_denial_mask2;
+ unsigned int c2c_ctrl;
+ unsigned char res2[0x1d8];
+ unsigned int central_seq_config;
+ unsigned int res3;
+ unsigned int central_seq_option;
+ unsigned char res4[0x1f4];
+ unsigned int swreset;
+ unsigned int rst_stat;
+ unsigned int auto_wdt_reset_disable;
+ unsigned int mask_wdt_reset_request;
+ unsigned char res5[0x1f0];
+ unsigned int wakeup_stat;
+ unsigned int eint_wakeup_mask;
+ unsigned int wakeup_mask;
+ unsigned char res6[0xf4];
+ unsigned int hdmi_phy_control;
+ unsigned int usbdevice_phy_control;
+ unsigned int hsic_1_phy_control;
+ unsigned int hsic_2_phy_control;
+ unsigned int mipi_phy0_control;
+ unsigned int mipi_phy1_control;
+ unsigned int adc_phy_control;
+ unsigned char res7[0x64];
+ unsigned int body_bias_con0;
+ unsigned int body_bias_con1;
+ unsigned int body_bias_con2;
+ unsigned int body_bias_con3;
+ unsigned char res8[0x70];
+ unsigned int inform0;
+ unsigned int inform1;
+ unsigned int inform2;
+ unsigned int inform3;
+ unsigned int inform4;
+ unsigned int inform5;
+ unsigned int inform6;
+ unsigned int inform7;
+ unsigned char res9[0x1e0];
+ unsigned int pmu_debug;
+ unsigned char res10[0x5fc];
+ unsigned int arm_core0_sys_pwr_reg;
+ unsigned char res11[0xc];
+ unsigned int arm_core1_sys_pwr_reg;
+ unsigned char res12[0x6c];
+ unsigned int arm_common_sys_pwr_reg;
+ unsigned char res13[0x3c];
+ unsigned int arm_cpu_l2_0_sys_pwr_reg;
+ unsigned int arm_cpu_l2_1_sys_pwr_reg;
+ unsigned char res14[0x38];
+ unsigned int cmu_aclkstop_sys_pwr_reg;
+ unsigned int cmu_sclkstop_sys_pwr_reg;
+ unsigned char res15[0x4];
+ unsigned int cmu_reset_sys_pwr_reg;
+ unsigned char res16[0x10];
+ unsigned int apll_sysclk_sys_pwr_reg;
+ unsigned int mpll_sysclk_sys_pwr_reg;
+ unsigned int vpll_sysclk_sys_pwr_reg;
+ unsigned int epll_sysclk_sys_pwr_reg;
+ unsigned char res17[0x8];
+ unsigned int cmu_clkstop_gps_alive_sys_pwr_reg;
+ unsigned int cmu_reset_gps_alive_sys_pwr_reg;
+ unsigned int cmu_clkstop_cam_sys_pwr_reg;
+ unsigned int cmu_clkstop_tv_sys_pwr_reg;
+ unsigned int cmu_clkstop_mfc_sys_pwr_reg;
+ unsigned int cmu_clkstop_g3d_sys_pwr_reg;
+ unsigned int cmu_clkstop_lcd0_sys_pwr_reg;
+ unsigned int cmu_clkstop_isp_sys_pwr_reg;
+ unsigned int cmu_clkstop_maudio_sys_pwr_reg;
+ unsigned int cmu_clkstop_gps_sys_pwr_reg;
+ unsigned int cmu_reset_cam_sys_pwr_reg;
+ unsigned int cmu_reset_tv_sys_pwr_reg;
+ unsigned int cmu_reset_mfc_sys_pwr_reg;
+ unsigned int cmu_reset_g3d_sys_pwr_reg;
+ unsigned int cmu_reset_lcd0_sys_pwr_reg;
+ unsigned int cmu_reset_isp_sys_pwr_reg;
+ unsigned int cmu_reset_maudio_sys_pwr_reg;
+ unsigned int cmu_reset_gps_sys_pwr_reg;
+ unsigned int top_bus_sys_pwr_reg;
+ unsigned int top_retention_sys_pwr_reg;
+ unsigned int top_pwr_sys_pwr_reg;
+ unsigned char res18[0x14];
+ unsigned int logic_reset_sys_pwr_reg;
+ unsigned char res19[0x1c];
+ unsigned int onenandxl_mem_sys_pwr_reg;
+ unsigned int hsi_mem_sys_pwr_reg;
+ unsigned char res20[0x4];
+ unsigned int usbotg_mem_sys_pwr_reg;
+ unsigned int sdmmc_mem_sys_pwr_reg;
+ unsigned int cssys_mem_sys_pwr_reg;
+ unsigned int secss_mem_sys_pwr_reg;
+ unsigned int potator_mem_sys_pwr_reg;
+ unsigned char res21[0x20];
+ unsigned int pad_retention_dram_sys_pwr_reg;
+ unsigned int pad_retention_maudio_sys_pwr_reg;
+ unsigned char res22[0x18];
+ unsigned int pad_retention_gpio_sys_pwr_reg;
+ unsigned int pad_retention_uart_sys_pwr_reg;
+ unsigned int pad_retention_mmca_sys_pwr_reg;
+ unsigned int pad_retention_mmcb_sys_pwr_reg;
+ unsigned int pad_retention_ebia_sys_pwr_reg;
+ unsigned int pad_retention_ebib_sys_pwr_reg;
+ unsigned char res23[0x8];
+ unsigned int pad_isolation_sys_pwr_reg;
+ unsigned char res24[0x1c];
+ unsigned int pad_alv_sel_sys_pwr_reg;
+ unsigned char res25[0x1c];
+ unsigned int xusbxti_sys_pwr_reg;
+ unsigned int xxti_sys_pwr_reg;
+ unsigned char res26[0x38];
+ unsigned int ext_regulator_sys_pwr_reg;
+ unsigned char res27[0x3c];
+ unsigned int gpio_mode_sys_pwr_reg;
+ unsigned char res28[0x3c];
+ unsigned int gpio_mode_maudio_sys_pwr_reg;
+ unsigned char res29[0x3c];
+ unsigned int cam_sys_pwr_reg;
+ unsigned int tv_sys_pwr_reg;
+ unsigned int mfc_sys_pwr_reg;
+ unsigned int g3d_sys_pwr_reg;
+ unsigned int lcd0_sys_pwr_reg;
+ unsigned int isp_sys_pwr_reg;
+ unsigned int maudio_sys_pwr_reg;
+ unsigned int gps_sys_pwr_reg;
+ unsigned int gps_alive_sys_pwr_reg;
+ unsigned char res30[0xc5c];
+ unsigned int arm_core0_configuration;
+ unsigned int arm_core0_status;
+ unsigned int arm_core0_option;
+ unsigned char res31[0x74];
+ unsigned int arm_core1_configuration;
+ unsigned int arm_core1_status;
+ unsigned int arm_core1_option;
+ unsigned char res32[0x37c];
+ unsigned int arm_common_option;
+ unsigned char res33[0x1f4];
+ unsigned int arm_cpu_l2_0_configuration;
+ unsigned int arm_cpu_l2_0_status;
+ unsigned char res34[0x18];
+ unsigned int arm_cpu_l2_1_configuration;
+ unsigned int arm_cpu_l2_1_status;
+ unsigned char res35[0xa00];
+ unsigned int pad_retention_maudio_option;
+ unsigned char res36[0xdc];
+ unsigned int pad_retention_gpio_option;
+ unsigned char res37[0x1c];
+ unsigned int pad_retention_uart_option;
+ unsigned char res38[0x1c];
+ unsigned int pad_retention_mmca_option;
+ unsigned char res39[0x1c];
+ unsigned int pad_retention_mmcb_option;
+ unsigned char res40[0x1c];
+ unsigned int pad_retention_ebia_option;
+ unsigned char res41[0x1c];
+ unsigned int pad_retention_ebib_option;
+ unsigned char res42[0x160];
+ unsigned int ps_hold_control;
+ unsigned char res43[0xf0];
+ unsigned int xusbxti_configuration;
+ unsigned int xusbxti_status;
+ unsigned char res44[0x14];
+ unsigned int xusbxti_duration;
+ unsigned int xxti_configuration;
+ unsigned int xxti_status;
+ unsigned char res45[0x14];
+ unsigned int xxti_duration;
+ unsigned char res46[0x1dc];
+ unsigned int ext_regulator_duration;
+ unsigned char res47[0x5e0];
+ unsigned int cam_configuration;
+ unsigned int cam_status;
+ unsigned int cam_option;
+ unsigned char res48[0x14];
+ unsigned int tv_configuration;
+ unsigned int tv_status;
+ unsigned int tv_option;
+ unsigned char res49[0x14];
+ unsigned int mfc_configuration;
+ unsigned int mfc_status;
+ unsigned int mfc_option;
+ unsigned char res50[0x14];
+ unsigned int g3d_configuration;
+ unsigned int g3d_status;
+ unsigned int g3d_option;
+ unsigned char res51[0x14];
+ unsigned int lcd0_configuration;
+ unsigned int lcd0_status;
+ unsigned int lcd0_option;
+ unsigned char res52[0x14];
+ unsigned int isp_configuration;
+ unsigned int isp_status;
+ unsigned int isp_option;
+ unsigned char res53[0x34];
+ unsigned int gps_configuration;
+ unsigned int gps_status;
+ unsigned int gps_option;
+ unsigned char res54[0x14];
+ unsigned int gps_alive_configuration;
+ unsigned int gps_alive_status;
+ unsigned int gps_alive_option;
+};
+
struct exynos4412_power {
unsigned char res1[0x0704];
unsigned int usbhost_phy_control;
- 修改power.c
因为itop4412 scp 核心板的电源管理是通过gpio来控制电源管理的，所以要将GPX0PUD寄存器设置为上拉模式。
diff --git a/arch/arm/mach-exynos/power.c b/arch/arm/mach-exynos/power.c
index c923460..caa81b7 100644
--- a/arch/arm/mach-exynos/power.c
+++ b/arch/arm/mach-exynos/power.c
@@ -163,6 +163,27 @@ static void exynos5_set_ps_hold_ctrl(void)
EXYNOS_PS_HOLD_CONTROL_DATA_HIGH);
}
+#ifdef CONFIG_ITOP4412
+static void exynos4x12_set_ps_hold_ctrl(void)
+{
+ struct exynos4x12_power *power =
+ (struct exynos4x12_power *)samsung_get_base_power();
+
+ /* value: 1000000000B */
+ setbits_le32(&power->ps_hold_control, EXYNOS_PS_HOLD_CONTROL_DATA_HIGH);
+
+ /**
+ * GPX0PUD register
+ *
+ * 0x0 = Disables Pull-up/Pull-down
+ * 0x1 = Enables Pull-down
+ * 0x2 = Reserved
+ * 0x3 = Enables Pull-up
+ */
+ writel(0x3, (unsigned int *)0x11000c08);
+}
+#endif
+
/*
* Set ps_hold data driving value high
* This enables the machine to stay powered on
@@ -173,6 +194,10 @@ void set_ps_hold_ctrl(void)
{
if (cpu_is_exynos5())
exynos5_set_ps_hold_ctrl();
+#ifdef CONFIG_ITOP4412
+ else if (cpu_is_exynos4())
+ exynos4x12_set_ps_hold_ctrl();
+#endif
}
8. 修改spl_boot.c
只有exynos5才需要调用emmc_boot_clk_div_set()接口，用宏控制。
diff --git a/arch/arm/mach-exynos/spl_boot.c b/arch/arm/mach-exynos/spl_boot.c
index 7df0102..42739de 100644
--- a/arch/arm/mach-exynos/spl_boot.c
+++ b/arch/arm/mach-exynos/spl_boot.c
@@ -229,8 +229,10 @@ void copy_uboot_to_ram(void)
#ifdef CONFIG_SUPPORT_EMMC_BOOT
case BOOT_MODE_EMMC:
/* Set the FSYS1 clock divisor value for EMMC boot */
+#ifndef CONFIG_ITOP4412
+ /* just for exynos5 can be call */
emmc_boot_clk_div_set();
-
+#endif
copy_bl2_from_emmc = get_irom_func(EMMC44_INDEX);
end_bootop_from_emmc = get_irom_func(EMMC44_END_INDEX);
9.修改板级头文件itop4412.h
起初拷贝的origen开发板的宏定义很多和itop4412开发板的不一样，需要做相应修改。如下：
diff --git a/include/configs/itop4412.h b/include/configs/itop4412.h
index 69f6930..c071e02 100644
--- a/include/configs/itop4412.h
+++ b/include/configs/itop4412.h
@@ -1,36 +1,39 @@
/*
* Copyright (C) 2011 Samsung Electronics
*
- * Configuration settings for the SAMSUNG ORIGEN (EXYNOS4210) board.
+ * Configuration settings for the SAMSUNG ITOP4412 (EXYNOS4412) board.
*
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef __CONFIG_ORIGEN_H
-#define __CONFIG_ORIGEN_H
+#ifndef __CONFIG_ITOP4412_H
+#define __CONFIG_ITOP4412_H
#include <configs/exynos4-common.h>
+#define CONFIG_SUPPORT_EMMC_BOOT 1
+
/* High Level Configuration Options */
-#define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */
-#define CONFIG_ORIGEN 1 /* working with ORIGEN*/
+#define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */
+#define CONFIG_ITOP4412 1 /* working with ITOP4412*/
#define CONFIG_SYS_DCACHE_OFF 1
-/* ORIGEN has 4 bank of DRAM */
+/* itop-4412 has 4 bank of DRAM */
#define CONFIG_NR_DRAM_BANKS 4
#define CONFIG_SYS_SDRAM_BASE 0x40000000
-#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
-#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
+#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
+#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000)
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x00100000)
#define CONFIG_SYS_TEXT_BASE 0x43E00000
-#define CONFIG_MACH_TYPE MACH_TYPE_ORIGEN
+/* #define MACH_TYPE_ITOP4412 0xffffffff */
+#define CONFIG_MACH_TYPE MACH_TYPE_ITOP4412
/* select serial console configuration */
#define CONFIG_SERIAL2
@@ -50,8 +53,8 @@
#define CONFIG_SUPPORT_RAW_INITRD
/* MMC SPL */
-#define COPY_BL2_FNPTR_ADDR 0x02020030
-#define CONFIG_SPL_TEXT_BASE 0x02021410
+#define COPY_BL2_FNPTR_ADDR 0x02020030
+#define CONFIG_SPL_TEXT_BASE 0x02023400 /* 0x02021410 */
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x40007000\0" \
@@ -61,12 +64,15 @@
"console=ttySAC2,115200n8\0" \
"mmcdev=0\0" \
"bootenv=uEnv.txt\0" \
+ "dtb_addr=0x41000000\0" \
+ "dtb_name=exynos4412-itop-4412.dtb\0" \
"loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
+ "bootargs=console=ttySAC2,115200n8 earlyprintk\0" \
"importbootenv=echo Importing environment from mmc ...; " \
- "env import -t $loadaddr $filesize\0" \
- "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \
- "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
- "source ${loadaddr}\0"
+ "env import -t $loadaddr $filesize\0" \
+ "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+ "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
+ "source ${loadaddr}\0"
#define CONFIG_BOOTCOMMAND \
"if mmc rescan; then " \
"echo SD/MMC found on device ${mmcdev};" \
@@ -82,7 +88,8 @@
"run bootscript; " \
"fi; " \
"fi;" \
- "load mmc ${mmcdev} ${loadaddr} uImage; bootm ${loadaddr} "
+ "mmc read ${loadaddr} 0x1000 0x4000; mmc read ${dtb_addr} 0x800 0xa0; bootm ${loadaddr} - ${dtb_addr}" \
+ "load mmc ${mmcdev} ${loadaddr} uImage; load mmc ${mmcdev} ${dtb_addr} ${dtb_name}; bootm ${loadaddr} - ${dtb_addr}"
#define CONFIG_CLK_1000_400_200
@@ -90,18 +97,21 @@
#define CONFIG_MIU_2BIT_21_7_INTERLEAVED
#define CONFIG_SYS_MMC_ENV_DEV 0
-#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
-#define RESERVE_BLOCK_SIZE (512)
-#define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
-#define CONFIG_ENV_OFFSET (RESERVE_BLOCK_SIZE + BL1_SIZE)
+#define CONFIG_ENV_SIZE (8 << 10) /* 16 KB */
+#define RESERVE_BLOCK_SIZE (512)
+#define BL1_SIZE (8 << 10) /*8 K reserved for BL1*/
+#define BL2_SIZE (16 << 10) /*16 K reserved for BL2 */
+#define CONFIG_ENV_OFFSET (RESERVE_BLOCK_SIZE + BL1_SIZE + BL2_SIZE)
#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024)
-#define CONFIG_SYS_INIT_SP_ADDR 0x02040000
+#define CONFIG_SPL_STACK 0x02040000
+#define UBOOT_SIZE (2 << 20)
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE+UBOOT_SIZE-0x1000)
-/* U-Boot copy size from boot Media to DRAM.*/
-#define COPY_BL2_SIZE 0x80000
-#define BL2_START_OFFSET ((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512)
-#define BL2_SIZE_BLOC_COUNT (COPY_BL2_SIZE/512)
+/* U-Boot copy size from boot Media to DRAM. */
+#define COPY_BL2_SIZE 0x80000
+#define BL2_START_OFFSET ((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512)
+#define BL2_SIZE_BLOC_COUNT (COPY_BL2_SIZE/512)
#endif /* __CONFIG_H */
Note: 由于文章内容过长，其余内容续接下一篇文章itop4412 uboot-2017.11移植（二）
)
网友评论