Note:
If you just want to modify code and compiling for E21 in U-Boot, please ignore step1~step7.⑥, and copy uboot_e21.tar from hapsxa1,then unzip this tar file under you home directory and do following step7.⑦

tar file: /home/haps01/git/u-boot-image/uboot_cmd/uboot_e21.tar
Computer Name: hapsxa1
IP address: 10.13.1.72
username: haps01

1. add gcc options for RV32.

   [图片上传失败...(image-3aa0b7-1582785535508)]

Add –march=rv32imac –mabi=ilp32 in u_boot.inc file as below:

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2. bitbake compile to produce new run.do_compile command.

[图片上传失败...(image-786095-1582785535508)]

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3. When the compile complete, run.do_compile for RV32 is created under /home/ningchunyang/SiFive-OE/riscv-sifive/build/tmp-glibc/work/freedom_u540-oe-linux/u-boot/1_2019.07-r0/temp/.

4. modify below files for E21. in /home/ningchunyang/SiFive-OE/riscv-sifive/build/tmp-glibc/work/freedom_u540-oe-linux/u-boot/1_2019.07-r0/:

> 1. git/include/configs/sifive-fe210.h
> 2. git/configs/sifive_fe210_defconfig
> 3. git/arch/riscv/Kconfig
> 4. git/board/sifive/fe210/fe210.c,Kconfig,Makefile
> 5. build/arch/riscv/dts 
     Modify design.dts according to E21 memory map and compile: [图片上传失败...(image-53f085-1582785535508)]

⑹ update .config  by menuconfig

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5. remove all the atomic instructions in git/arch/riscv/cpu/start.S because the RAM is attached to system port and this port can’t support atomic operation.

6. Till now , all the configurations for E21 are prepared. And we won’t run bitbake command, but run ./run.do_compile under temp to compile, otherwise some configuration will restore to the older.

7. if you hope to have a short path to compile, then create a uboot_e21 folder for E21 code under u-boot.

1. mkdir /home/ningchunyang/uboot_e21/

2. cp -r /home/ningchunyangg/SiFive-OE/riscv-sifive/build/tmp-glibc/work/freedom_u540-oe-linux/u-boot/1_2019.07-r0/git /home/ningchunyangg /uboot_e21/

3. mv /home/ningchunyangg /uboot_e21/git /home/ningchunyangg /uboot_e21/src/

4. mkdir /home/ningchunyangg /uboot_e21/build/

5. cp /home/ningchunyang /SiFive-OE/riscv-sifive/build/tmp-glibc/work/freedom_u540-oe-linux/u-boot/1_2019.07-r0/build/ .config /home/ningchunyang/uboot_e21/build/

6. cp –r /home/ningchunyang /SiFive-OE/riscv-sifive/build/tmp-glibc/work/freedom_u540-oe-linux/u-boot/1_2019.07-r0/temp /home/ningchunyang/uboot_e21/

7. modify the path in /home/ningchunyang/uboot_e21/temp/run.do_compile, just replace “ningchunyang” with your name .

8. the first time when you compile, if there is an error that device tree file can’t be found.

cp /home/ningchunyang /SiFive-OE/riscv-sifive/build/tmp-glibc/work/freedom_u540-oe-linux/u-boot/1_2019.07-r0/build/arch/riscv/dts/design.dtb /home/ningchunyang/uboot_e21/build/ arch/riscv/dts/design.dtb

9. . ./run.do_compile

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8. note:

①should set arch riscv:rv32 before “target remote” if debug with gdb.

② can’t enable CONFIG_CC_OPTIMIZE_FOR_SIZE in .config. other the 32bit linker can’t identify “<<” and“>>” operation.

③if the RAM is attached to peripheral port , the atomic instruction removed in step 5 can be recovered.

④E21 has CLIC interrupt controller, but it can’t support under u-boot, now I define it as CLINT.

tar file location

• tar file: /home/haps01/git/u-boot-image/uboot_cmd/uboot_e21.tar
  Computer Name: hapsxa1
  IP address:10.13.1.72
  username: haps01
  password: xxx(ask me)

---

steps to compile

1. scp haps01@10.13.1.72:/home/haps01/git/u-boot-image/uboot_cmd/uboot_e21.tar .
2. tar xf uboot_e21.tar
3. cd uboot_e21/temp
4. ./run.do_compile

---# steps to start toolchain：

1. config HAPS for E21
   1.1 通过confpro_gui 对HAPS 进行配置，选择：
   /home/zzq/Public/haps_release/work_E21_NOC_0204_1/confpro/prj_conf_auto/designs/project.conf
   1.2 cd /home/zzq/Public/haps_release/test_script/
   1.3 confprosh load_e21openocd.tcl 允许通过openocd debug
2. openocd: /home/haps01/git/freedom-e-sdk/toolchain/centos/riscv-openocd-0.10.0-2019.08.2-x86_64-linux-centos6
   ./openocd -f openocd_E21.cfg 启动 openocd
3. gdb: /home/haps01/git/freedom-e-sdk/toolchain/centos/riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-linux-centos6/bin
   3.1 ./riscv64-unknown-elf-gdb 启动gdb
   3.2 source init-for-e21.gdb 配置gdb为32-bit，来支持E21
   3.3 file /home/haps01/git/u-boot-image/uboot_cmd/uboot_e21/u-boot 指定要debug/run的文件
   3.4 source standard-sequence.gdb load file到haps