实验5-3:74LS138设计3:8译码器(行为描述)
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:41:01 11/15/2018
// Design Name:
// Module Name: Trial_53
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Trial_53(
A,B,C,Y,G1,G2A,G2B
);
input wire A,B,C;
input wire G1,G2A,G2B;
output reg [7:0] Y;
always @(*)
begin
Y=8'b11111111;
if (G1&(~G2A)&(~G2B))
begin
if((~A)&(~B)&(~C)) Y[0]=0;
else if((~A)&(~B)&(C)) Y[1]=0;
else if((~A)&(B)&(~C)) Y[2]=0;
else if((~A)&(B)&(C)) Y[3]=0;
else if((A)&(~B)&(~C)) Y[4]=0;
else if((A)&(~B)&(C)) Y[5]=0;
else if((A)&(B)&(~C)) Y[6]=0;
else if((A)&(B)&(C)) Y[7]=0;
end
end
endmodule
管脚约束文件
NET "G1" IOSTANDARD = LVCMOS18;
NET "G2A" IOSTANDARD = LVCMOS18;
NET "G2B" IOSTANDARD = LVCMOS18;
NET "C" IOSTANDARD = LVCMOS18;
NET "B" IOSTANDARD = LVCMOS18;
NET "A" IOSTANDARD = LVCMOS18;
NET "A" LOC = W4;
NET "B" LOC = V4;
NET "C" LOC = V3;
NET "G1" LOC = T3;
NET "G2A" LOC = U3;
NET "G2B" LOC = T4;
NET "Y[7]" IOSTANDARD = LVCMOS18;
NET "Y[6]" IOSTANDARD = LVCMOS18;
NET "Y[5]" IOSTANDARD = LVCMOS18;
NET "Y[4]" IOSTANDARD = LVCMOS18;
NET "Y[3]" IOSTANDARD = LVCMOS18;
NET "Y[2]" IOSTANDARD = LVCMOS18;
NET "Y[1]" IOSTANDARD = LVCMOS18;
NET "Y[0]" IOSTANDARD = LVCMOS18;
NET "Y[7]" LOC = R1;
NET "Y[6]" LOC = P2;
NET "Y[5]" LOC = P1;
NET "Y[4]" LOC = N2;
NET "Y[3]" LOC = M1;
NET "Y[2]" LOC = M2;
NET "Y[1]" LOC = L1;
NET "Y[0]" LOC = J2;
NET "G1" PULLDOWN;
NET "G2A" PULLDOWN;
NET "G2B" PULLDOWN;
NET "C" PULLDOWN;
NET "B" PULLDOWN;
NET "A" PULLDOWN;
网友评论