QEMU

QEMU is a generic and open source machine emulator and virtualizer.

libsystemctlm-soc

You do not need to interface directly with Remote-Port. Xilinx provides abstractions for SystemC/TLM-2.0 that encapsulate your SystemC/TLM-2.0 module, allowing it to connect to remote QEMU instances. These modules use Remote-Port. SystemC/TLM-2.0 users can, therefore, treat QEMU as any other standard SystemC/TLM-2.0 module. These abstractions are in the libsystemctlm-soc repository. For an example of wrapping your SystemC application, see the SystemC/TLM-2.0 co-simulation demonstration.

ug1169-xilinx-qemu.pdf • 查看器 • AMD 自适应计算文档门户

SystemC

systemc.org

SystemC™ addresses the need for a system design and verification language that spans hardware and software. It is a language built in standard C++ by extending the language with the use of class libraries. The language is particularly suited to model system's partitioning, to evaluate and verify the assignment of blocks to either hardware or software implementations, and to architect and measure the interactions between and among functional blocks. Leading companies in the intellectual property (IP), electronic design automation (EDA), semiconductor, electronic systems, and embedded software industries currently use SystemC for architectural exploration, to deliver high-performance hardware blocks at various levels of abstraction and to develop virtual platforms for hardware/software co-design. SystemC has been standardized by the Open SystemC Initiative (OSCI) and Accellera Systems Initiative and ratified as IEEE Std. 1666™-2011.

架构探索，快速建模。很好、很强大！

Chisel

Chisel/FIRRTL: Home (chisel-lang.org)

The Constructing Hardware in a Scala Embedded Language (Chisel) is an open-source hardware description language (HDL) used to describe digital electronics and circuits at the register-transfer level that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs.

Chisel adds hardware construction primitives to the Scala programming language, providing designers with the power of a modern programming language to write complex, parameterizable circuit generators that produce synthesizable Verilog. This generator methodology enables the creation of re-usable components and libraries, such as the FIFO queue and arbiters in the Chisel Standard Library, raising the level of abstraction in design while retaining fine-grained control.

For more information on the benefits of Chisel see: “What benefits does Chisel offer over classic Hardware Description Languages?”

Chisel is powered by FIRRTL (Flexible Intermediate Representation for RTL), a hardware compiler framework implemented by LLVM CIRCT.

揭秘“香山”：高性能开源RISC-V处理器 | 对话中科院计算所包云岗研究员 | Shilicon Talk第一期_哔哩哔哩_bilibili

香山团队说用着很爽，可以一试！

Verilator

Veripool

Welcome to Verilator, the fastest Verilog/SystemVerilog simulator.

Accepts Verilog or SystemVerilog
Performs lint code-quality checks
Compiles into multithreaded C++, or SystemC
Creates XML to front-end your own tools

使用 SystemC 对 GPU 建模，其中的模块 A 建模完成后将其使用硬件描述语言实现，实现完成后将其集成到 SystemC 模型中，替换原先的模块 A，迅速验证模块 A 的功能。这个过程需要用到 Verilator。

Verilog-mode

Verilog-Mode · Veripool

Verilog-mode.el is the extremely popular free Verilog mode for Emacs which provides context-sensitive highlighting, auto indenting, and provides macro expansion capabilities to greatly reduce Verilog coding time. It supports AUTOs and indentation in Emacs for traditional Verilog (1394-2005), the Open Verification Methodology (OVM) and SystemVerilog (1800-2005/1800-2009).

Verilog-mode also allows you to insert AUTOS in non-AUTO designs, so IP interconnect can be easily modified. You can also expand SystemVerilog ".*" port instantiations, to see what ports will be connected by the simulators.

自动连线、自动实例化等功能非常好用。