UART接收器设计

时序图 状态转移表

//采用16倍波特率的时钟信号，在每个位的中间时刻进行采样
module UartRecv(input Clk_x,DataIn,output reg [7:0]DataOut,output reg DataReady);
    
    // BitRate = Clk_x / (Multi+1)
    parameter Multi = 4'b1111;
    // State Parameter
    parameter Idle = 2'd0;
    parameter Recv = 2'd1;
    parameter CheckByte = 2'd2;
    parameter CheckStop = 2'd3;
    
    reg [3:0] ClkCount;
    reg [3:0] BitCount;
    reg [1:0] State;
    reg [8:0] Buffer;
    
    always @(posedge Clk_x)
    begin
        if(State == Idle)
        begin
            BitCount <=0;
            Buffer <=0;
            DataReady <=0;
            
            if(DataIn == 1)
            begin
                ClkCount <=0;               
                State <= Idle;
            end
            else // if(DataIN == 0)
            begin               
                if(ClkCount ==7)
                begin
                    ClkCount <=0;
                    State <= Recv;
                end
                else// if (ClkCount <7)
                begin
                    ClkCount <= ClkCount+1'd1;              
                    State <= Idle;
                end                 
            end
        end
        else if(State == Recv)
        begin
            ClkCount<=ClkCount+1'b1;    
            DataReady <=0;
                    
            if (ClkCount==15) 
            begin
                BitCount <= BitCount+1'b1;
                Buffer[BitCount]<=DataIn;
                State <= CheckByte;
            end
            else State <= Recv;
        end
        else if(State == CheckByte)
        begin
            ClkCount<=ClkCount+1'b1;            
            if (BitCount==9) State <= CheckStop;
            else State <= Recv;
        end
        else if(State == CheckStop)
        begin   
            State <= Idle;
                    
            if (DataIn==1) 
            begin
                DataOut<=Buffer[7:0];
                DataReady <=1;
            end
        end
    end
endmodule