Verilog的代码编写完成了,代码是否正确,需要经过仿真的验证。
打开FreDivDou的工程,
![](https://img.haomeiwen.com/i17129331/5f7d734384b9ebb2.png)
点击Sources中的“+”,
![](https://img.haomeiwen.com/i17129331/f77dafd29dcbfc85.png)
选择添加仿真文件,点击“Next”,
![](https://img.haomeiwen.com/i17129331/0e17a44c6cef2e24.png)
点击“Create File”,
![](https://img.haomeiwen.com/i17129331/0b41708cd6811f60.png)
File Type选择Verilog,File name填写仿真文件名称,点击OK,
![](https://img.haomeiwen.com/i17129331/745da9042ac77ced.png)
点击Finish,
![](https://img.haomeiwen.com/i17129331/028ed0ce9db92542.png)
点击OK,
![](https://img.haomeiwen.com/i17129331/d85ee1043c37d920.png)
点击Yes,
![](https://img.haomeiwen.com/i17129331/9bf2c8693f0e4b31.png)
成了仿真文件tb_Fre.v,双击tb_Fre(tb_Fre.v),
![](https://img.haomeiwen.com/i17129331/fd5ae435980b0eda.png)
在tb_Fre.v中编写仿真代码,
moduletb_Fre(
);
reg clk_i;
reg rst_n_i;
wire div2_o;
wire div3_o;
wire div4_o;
wire dou2_o;
wire dou3_o;
FreDivDouttb( //调用FreDivDou.v
.clk_i(clk_i), //.后面的clk_i是FreDivDou.v中的端口名称,括号内的clk_i是仿
//真文件tb_Fre.v中定义的变量名称
.rst_n_i(rst_n_i),
.div2_o(div2_o),
.div3_o(div3_o),
.div4_o(div4_o),
.dou2_o(dou2_o),
.dou3_o(dou3_o)
);
//initial块从仿真0时刻开始执行,在整个仿真过程中只执行一次
initial begin
clk_i = 0;
rst_n_i = 0;
#1000;
rst_n_i = 'b1;
end
//产生一个周期为20ns的时钟
always #10 clk_i = ~clk_i;
endmodule
仿真代码编写完成后,保存该文件,
![](https://img.haomeiwen.com/i17129331/105f29c25451fc75.png)
点击PROJECT MANAGER——SIMULATION——Run Simulation,
![](https://img.haomeiwen.com/i17129331/79085a39f73de5bd.png)
点击Run Behavior Simulation,
![](https://img.haomeiwen.com/i17129331/f45ecb8af34f621a.png)
等待若干秒钟,
![](https://img.haomeiwen.com/i17129331/9d9cd7b4fa8b5300.png)
点击仿真界面的最大化按钮,如上图所示,
![](https://img.haomeiwen.com/i17129331/38a1e332e666c232.png)
点击上图中的Run All按钮,开始仿真,
![](https://img.haomeiwen.com/i17129331/74dc7e169b0250b6.png)
数一数,你就会发现,假定clk_i是50M时钟,那么div2_o的时钟是50M/2=25M;div3_o的时钟是50M/3=16.67M;div4_o的时钟是50M/4=12.5M;dout2_o的时钟是50M*2=100M;dout3_o的时钟是50M*3=150M。
网友评论