实验5-1：五输入表决器（门级结构描述）

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    14:16:00 11/08/2018 
// Design Name: 
// Module Name:    Trial_51 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Trial_51 (A,B,C,D,E,F);
    input A,B,C,D,E;
    output F;
    wire A,B,C,D,E,F;
    //assign F = (A&B&C)|(A&D&E)|(A&C&E)|(A&C&D)|(A&B&E)|(A&B&D)|((~A)&B&C&E)|((~A)&B&C&D)|((~A)&B&D&E)|((~A)&C&D&E);
    
    wire s1,s2,s3,s4,s5;
    
    or OU1(s1,B,C),
       OU2(s2,D,E);
    and AU1(s3,B,C),
        AU2(s4,D,E);
    not NU1(s5,A);
    
    wire f1,f2;
    and AU3(f1,s5,s3,s2),
        AU4(f2,s5,s1,s4);
    
    wire m1;
    and AU5(m1,s1,s2);
    
    wire m2;
    or OU3(m2,s3,s4,m1);
    
    wire f3;
    and AU6(f3,m2,A);
    
    or OU4(F,f1,f2,f3);
    
    
endmodule

管脚约束文件

# PlanAhead Generated physical constraints 
NET "A"   LOC = T3;     //SW1
NET "B"   LOC = U3;     //SW2
NET "C"   LOC = T4;     //SW3
NET "D"   LOC = V3;     //SW4
NET "E"   LOC = V4;     //SW5

NET "F"   LOC = R1; //LED01



NET "A"  IOSTANDARD = LVCMOS18; 
NET "B"  IOSTANDARD = LVCMOS18; 
NET "C"  IOSTANDARD = LVCMOS18; 
NET "D"  IOSTANDARD = LVCMOS18; 
NET "E"  IOSTANDARD = LVCMOS18;

NET "F"  IOSTANDARD = LVCMOS18; 

NET "A"  PULLDOWN; 
NET "B"  PULLDOWN;  
NET "C"  PULLDOWN;  
NET "D"  PULLDOWN; 
NET "E"  PULLDOWN;