3年经验
1. Brief Introduction and major projects?
2. Tell me the most challenging part of your recent project
3. How does the lockup latch help to fix hold violations?
4. If we add a lockup latch, it might violate the setup? How will we fix it further?
5. How did you fix SigEM? What are patch wires?
6. What CTS constraints have you used?
7. How did you fix the setup violation?
8. Apart from setup and hold, what other checks do we perform in timing signoff?
9. What are the PV checks?
10. What are the sanity checks we do before starting PnR?
11. What are the reports of synthesis we check before PnR?
12. What are the physical cells we have used in PD and what are the uses of all
those?
13. What is the latch-up issue and how well tap cells prevent latchup?
14. What is the endCap cell and what is the purpose of using that?
15. What is Dcap Cell and why do we use it?
16. What is the antenna effect?
17. What are the ways to fix the antenna effect?
18. How do antenna diodes help to fix the antenna violations?
19. If we have timing criticality and we can't use antenna diodes or floating gates,
How can we fix the antenna?
20. If antenna violation is already the highest metal layer and we can use higher
metal for metal hopping, how will fix the antenna?
21. How will you fix the antenna violations on via?
22. What is a metal cut layer?
23. What is the crosstalk delay?
24. What is the crosstalk noise?
1. What are the major differences between 7nm and 12/14nm technology nodes?
2. What are the new DRC rules in the 7nm technology node?
3. What is the via-piller?
4. What is double patterning?
5. How many layers have double patterning in the 7nm node?
6. How tool performs placement steps?
7. Why do we perform scan chain reordering?
8. What is scan mode, why do we need that?
9. What is ECF (Early Clock Flow) flow?
10. What are the benefits of ECF flow?
11. Can you explain the CTS flow?
12. What are the low power techniques used in data and clock paths?
13. Where does the clock-gater use?
14. Have you built a custom clock tree?
15. What are the constraints you have given to the clock tree?
16. How did you solve max_trans violations in the clock path?
17. How to provide different clock tap points in H-Tree?
18. How many clocks were there in your block?
19. How were they related?
20. How did you analyze the clock domain crossing paths?
21. What is a lock-up latch and how does it helps in hold fixing?
22. What was the target skew in your block?
23. What value of skew you achieved?
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