Verilog 74HC__

作者: kekxy | 来源:发表于2020-12-17 22:12 被阅读0次

Verilog 74HC__
Verilog 语言简介
Verilog：基础语法（上）
PLI
Verilog DHL 学习笔记
verilog两种头模块头申明方式
【Verilog语言】Verilog语法基础
Verilog HDL 入门
Modsim 使用过程中出现的一些问题
systemverilog之Automatic(转)

//andnot.v
module andnot(a,b,y);
    input a,b;
    output reg y;

always@(a or b)
begin
    y <= ~(a&b);
end
endmodule


//testandnot.v
`timescale 1ns/ 1ns

module testandnot;
reg pa,pb;
wire y;

andnot u1(pa,pb,y);
initial
begin
    pa=0;pb=0;
    #5 pa=1;
    #5 pb=1;
    #5 pa=0;
    #5 pb=0;
end
initial
$monitor("time=%t,a=%b,b=%b,y=%b",$time,pa,pb,y);

endmodule

//hc148.v
module HC148(EI,I,A,EO,GS);
input [7:0] I;
input EI;
output [2:0] A;
reg [2:0] A;
output EO,GS;
reg EO,GS;
integer i;

always@(EI or I)
begin
    if (EI)
    begin
        A=7; EO=1; GS=1;
    end else
    if(I==8'b11111111)
    begin
        A=7; EO=0; GS=1;
    end
    else
    for(i=0;i<8;i=i+1)
    begin
    if(~I[i])
        begin
            A=~i; EO=1; GS=0;
        end
    end
end
endmodule


//testhc148.v
`timescale 1ns/1ns
module testhc148;
reg pEI;
reg [7:0] pI;
wire [2:0] pA;
wire pEO,pGS;
integer i;

HC148 u1(pEI,pI,pA,pEO,pGS);
initial
begin
    pEI=1; pI=0;
    #5 pEI=0;
    for(i=0;i<256;i=i+1)
    begin
        pI=~i;
        #5;
    end
end
initial
$monitor("$time=%t,EI=%b,I=%b,A=%b,EO=%b,GS=%b",$time,pEI,pI,pA,pEO,pGS);
endmodule

//hc138.v
module HC138(E1,E2,E3,I,A);
input E1,E2,E3;
input [2:0] I;
output [7:0] A;
reg [7:0] A;

always@(E1 or E2 or E3 or I)
begin
    if(E1==0 && E2==0 && E3==1)
    begin
        A=255;
        A[I]=0;
    end else A=255;
end

endmodule


//testhc138.v
`timescale 1ns/1ns
module testhc138;
reg pE1,pE2,pE3;
reg [2:0] pI;
wire [7:0] pA;
integer i;

HC138 u1(pE1,pE2,pE3,pI,pA);
initial
begin
    pE1=0; pE2=0; pE3=0;
    #5 pE1=0; pE2=1; pE3=0;
    #5 pE1=0; pE2=1; pE3=1;
    #5 pE1=1; pE2=0; pE3=0;
    #5 pE1=1; pE2=0; pE3=1;
    #5 pE1=1; pE2=1; pE3=0;
    #5 pE1=1; pE2=1; pE3=1;
    #5 pE1=0; pE2=0; pE3=1;
    for(i=0;i<8;i=i+1)
    begin
        pI=i; #10;
    end
end
initial
$monitor("$time=%t,pE1=%b,pE2=%b,pE3=%b,pI=%b,pA=%b",$time,pE1,pE2,pE3,pI,pA);
endmodule

//hc153.v
module HC153(E1,S1,I1,Y1,E2,S2,I2,Y2);
input E1,E2;
input [1:0] S1,S2;
input [3:0] I1,I2;
output Y1,Y2;
reg Y1,Y2;

always@(E1 or S1 or I1)
begin
    if(E1==1) Y1=1; else Y1=I1[S1];
end
always@(E2 or S2 or I2)
begin
    if(E2==1) Y2=1; else Y2=I2[S2];
end
endmodule

//testhc153.v
`timescale 1ns/1ns
module testhc153;
reg pE;
reg [1:0] pS;
reg [3:0] pI;
wire pY;
integer i;

HC153 u1(pE,pS,pI,pY,pE,pS,pI,pY);
initial
begin
    pE=1;
    #5 pE=0;
    for(i=0;i<4;i=i+1)
    begin
        pS=i;
        pI=1<<i;
        #5 pI=~pI; #5;
    end
end
initial
$monitor("$time=%t,E=%b,S=%b,I=%b,Y=%b",$time,pE,pS,pI,pY);
endmodule

//hc85.v
module HC85(A,B,I,Q);
input [3:0] A,B;
input [2:0] I;
output [2:0] Q;
reg [2:0] Q;

always@(A or B or I)
begin
    if(A>B) Q=4; else
    if(A<B) Q=1; else
    begin
        if(I[1]==1) Q=2; else
        if(I==0) Q=5; else
        if(I==5) Q=0; else Q=I;
    end
end
endmodule


//testhc85.v
`timescale 1ns/1ns
module testhc85;
reg [3:0] pA,pB;
reg [2:0] pI;
wire [2:0] pQ;
integer i,s;

HC85 u1(pA,pB,pI,pQ);
initial
begin
    pA=0; pB=0; s=0;
    for(i=3;i>=0;i=i-1)
    begin
        pA=s+(1<<i); pB=s+0;
        #5 pA=s; pB=s+(1<<i);
        #5 s=s+(1<<i);
    end
    pA=s; pB=s;
    for(i=0;i<8;i=i+1)
    begin
        pI=i;
        #5;
    end
end
initial
$monitor("$time=%t,A=%b,B=%b,I=%b,Q=%b",$time,pA,pB,pI,pQ);
endmodule

//hc283.v
module HC283(Ci,A,B,Co,S);
input [3:0] A,B;
input Ci;
output [3:0] S;
reg [3:0] S;
reg [3:0] G,P;
output Co;
reg Co;

always@(Ci or A or B)
begin
    G=A&B;
    P=A^B;
    Co=G[3]|(P[3]&G[2])|(P[3]&P[2]&G[1])|(P[3]&P[2]&P[1]&G[0])|(P[3]&P[2]&P[1]&P[0]&Ci);
    S[0]=P[0]^Ci;
    S[1]=P[1]^(G[0]|(P[0]&Ci));
    S[2]=P[2]^(G[1]|(P[1]&G[0])|(P[1]&P[0]&Ci));
    S[3]=P[3]^(G[2]|(P[2]&G[1])|(P[2]&P[1]&G[0])|(P[2]&P[1]&P[0]&Ci));
end
endmodule


//testhc283.v
`timescale 1ns/1ns
module testhc283;
reg [3:0] pA,pB;
reg pCi;
wire [3:0] pS;
wire [3:0] pG,pP;
wire pCo;

HC283 u1(pCi,pA,pB,pCo,pS);
initial
begin
    pCi=0; pA=4'b1101; pB=4'b1001; #5;
    pCi=1; pA=4'b0111; pB=4'b0101; #5;
end
initial
$monitor("$time=%t,Ci=%b,A=%b,B=%b,Ci=%b,S=%b",$time,pCi,pA,pB,pCo,pS);
endmodule

//hc4511.v
module HC4511(A,B,C);  //A[3]=LE BI LT B[3]=num C[0..6]=abcdefg
input [2:0] A;
input [3:0] B;
output [0:6] C;
reg [0:6] C;

always@(A or B)
begin
    if(A[0]==0) C=255; else
    if(A[1]==0 && A[0]==1) C=0; else
    if(A==3)
    begin
        if(B==0) C=7'b1111110; else
        if(B==1) C=7'b0110000; else
        if(B==2) C=7'b1101101; else
        if(B==3) C=7'b1111001; else
        if(B==4) C=7'b0110011; else
        if(B==5) C=7'b1011011; else
        if(B==6) C=7'b1011111; else
        if(B==7) C=7'b1110000; else
        if(B==8) C=7'b1111111; else
        if(B==9) C=7'b1111011; else
        if(B==10) C=7'b1110111; else
        if(B==11) C=7'b0011111; else
        if(B==12) C=7'b0001101; else
        if(B==13) C=7'b0111101; else
        if(B==14) C=7'b1001111; else
        if(B==15) C=7'b1000111;
    end
end
endmodule


//testhc4511.v
`timescale 1ns/1ns
module testhc4511;
reg [2:0] pA;
reg [3:0] pB;
wire [6:0] pC;
integer i;

HC4511 u1(pA,pB,pC);
initial
begin
    pA=0; #5;
    pA=1; #5;
    pA=3;
    for(i=0;i<16;i=i+1)
    begin
        pB=i; #5;
    end
end
initial
$monitor("$time=%t,LE=%b,BI=%b,LT=%b,B=%b,C=%b",$time,pA[2],pA[1],pA[0],pB,pC);
endmodule

//hc74.v
module HC74(s1,r1,clk1,d1,q1,p1,s2,r2,clk2,d2,q2,p2);
input s1,r1,s2,r2,clk1,clk2,d1,d2;
output q1,q2,p1,p2;
reg q1,q2,p1,p2;

always@(negedge s1 or negedge r1 or posedge clk1)
begin
    if(s1 && r1)
    begin
        q1=d1; p1=~q1;
    end else
    if(!s1 && r1)
    begin
        q1=1; p1=0;
    end else
    if(s1 && !r1)
    begin
        q1=0; p1=1;
    end
end

always@(negedge s2 or negedge r2 or posedge clk2)
begin
    if(s2 && r2)
    begin
        q2=d2; p2=~q2;
    end else
    if(!s2 && r2)
    begin
        q2=1; p2=0;
    end else
    if(s2 && !r2)
    begin
        q2=0; p2=1;
    end
end

endmodule


//testhc74.v
`timescale 1ns/1ns
module testhc74;
reg ps,pr,pclk,pd;
wire pq,pp;

HC74 u1(ps,pr,pclk,pd,pq,pp,ps,pr,pclk,pd,pq,pp);
initial
begin
    ps=0; pr=1; #10;
    ps=1; pr=0; #10;
    ps=1; pr=1; pd=1; #10;
    ps=1; pr=1; pd=0; #10;
    ps=0; pr=0; #10;

    ps=0; pr=1; #10;
    ps=1; pr=1; pd=0; #10;
    ps=1; pr=1; pd=1; #10;
    ps=0; pr=0; #10;
end
initial
begin
    pclk=0;
    forever #5 pclk=~pclk;
end
initial
$monitor("$time=%t,S=%b,R=%b,clk=%b,D=%b,Q=%b,!Q=%b",$time,ps,pr,pclk,pd,pq,pp);
endmodule

//hc112.v
module HC112(s1,r1,clk1,j1,k1,q1,p1,s2,r2,clk2,j2,k2,q2,p2);
input s1,r1,s2,r2,clk1,clk2,j1,k1,j2,k2;
output q1,q2,p1,p2;
reg q1,q2,p1,p2;

always@(negedge s1 or negedge r1 or negedge clk1)
begin
    if(s1 && r1)
    begin
        if(j1 && k1) begin q1=~q1; p1=~p1; end else
        if(j1 || k1) begin q1=j1; p1=k1; end
    end else
    if(!s1 && r1)
    begin
        q1=1; p1=0;
    end else
    if(s1 && !r1)
    begin
        q1=0; p1=1;
    end
end

always@(negedge s2 or negedge r2 or negedge clk2)
begin
    if(s2 && r2)
    begin
        if(j2 && k2) begin q2=~q2; p2=~p2; end else
        if(j2 || k2) begin q2=j2; p2=k2; end
    end else
    if(!s2 && r2)
    begin
        q2=1; p2=0;
    end else
    if(s2 && !r2)
    begin
        q2=0; p2=1;
    end
end

endmodule


//testhc112.v
`timescale 1ns/1ns
module testhc112;
reg ps,pr,pclk,pj,pk;
wire pq,pp;

HC112 u1(ps,pr,pclk,pj,pk,pq,pp,ps,pr,pclk,pj,pk,pq,pp);
initial
begin
    ps=0; pr=1; #10;
    ps=1; pr=0; #10;
    ps=1; pr=1; pj=1; pk=0; #10;
    ps=1; pr=1; pj=0; pk=1; #10;
    ps=1; pr=1; pj=1; pk=1; #10;
    ps=1; pr=1; pj=0; pk=0; #10;

    ps=0; pr=1; #10;
    ps=1; pr=1; pj=0; pk=1; #10;
    ps=1; pr=1; pj=1; pk=0; #10;
    ps=1; pr=1; pj=1; pk=1; #10;
    ps=1; pr=1; pj=0; pk=0; #10;
end
initial
begin
    pclk=0;
    forever #5 pclk=~pclk;
end
initial
$monitor("$time=%t,S=%b,R=%b,clk=%b,J=%b,K=%b,Q=%b,!Q=%b",$time,ps,pr,pclk,pj,pk,pq,pp);
endmodule

//hc161.v
module HC161(mr,clk,ep,et,pe,D,Q,tc);
input mr,clk,ep,et,pe;
input [3:0] D;
output tc;
reg tc;
output [3:0] Q;
reg [3:0] Q;

always@(negedge mr or posedge clk)
begin
    if(!mr) Q=0; else
    if(!pe) Q=D; else
    if(ep && et) Q=Q+1;
    tc=et&&Q[3]&&Q[2]&&Q[1]&&Q[0];
end
endmodule


//testhc161.v
`timescale 1ns/1ns
module testhc161;
reg [3:0] pD;
wire [3:0] pQ;
reg pmr,pclk,pep,pet,ppe;
wire ptc;
integer i;

HC161 u1(pmr,pclk,pep,pet,ppe,pD,pQ,Tc);
initial
begin
    pmr=0; #10;
    pmr=1; ppe=0; pD=4'b1111; #10;
    pmr=1; ppe=0; pD=4'b1000; #10;
    ppe=1; pep=1; pet=1;
    for(i=0;i<4;i=i+1) #10;
    pep=0; #10;
    pet=0; pep=1; #10;
    pmr=0; #10;
end

initial
begin
    pclk=0;
    forever #5 pclk=~pclk;
end
initial
$monitor("$time=%t,MR=%b,Clk=%b,Cep=%b,Cet=%b,PE=%b,D=%b,Q=%b,Tc=%b",
$time,pmr,pclk,pep,pet,ppe,pD,pQ,ptc);
endmodule

//hc194.v
module HC194(mr,S,clk,d,D,Q);//d[1]-Dsr d[0]-Dsl
input [1:0] S,d;
input mr,clk;
input [3:0] D;
output [3:0] Q;
reg [3:0] Q,P;

always@(negedge mr or posedge clk)
begin
    if(!mr) Q=0; else
    if(S==3) Q=D; else
    if(S==1)
    begin
        P=Q;
        Q[0]=d[1]; Q[1]=P[0]; Q[2]=P[1]; Q[3]=P[2];
    end else
    if(S==2)
    begin
        P=Q;
        Q[3]=d[0]; Q[2]=P[3]; Q[1]=P[2]; Q[0]=P[1];
    end
end
endmodule


//testhc194.v
`timescale 1ns/1ns
module testhc194;
reg [1:0] pS,pd;
reg pmr,pclk;
reg [3:0] pD;
wire [3:0] pQ;

HC194 u1(pmr,pS,pclk,pd,pD,pQ);
initial
begin
    pmr=0; #10;
    pmr=1; pS=3; pD=4'b1101; #10;
    pS=1; pd[1]=0; #10; pd[1]=1; #10;
    pS=2; pd[0]=0; #10; pd[0]=1; #10;
    pS=0; #10;
    pmr=0; #10;
end

initial
begin
    pclk=0;
    forever #5 pclk=~pclk;
end
initial
$monitor("$time=%t,MR=%b,S1=%b,S0=%b,Clk=%b,Dsr=%b,Dsl=%b,D=%b,Q=%b",
$time,pmr,pS[1],pS[0],pclk,pd[1],pd[0],pD,pQ);
endmodule

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